Altium Designer6.9 破解文件与模板
上传时间： 2015-01-01
上传用户：392210346
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
S7-300模板规范
上传时间： 2014-08-13
上传用户：pinksun9
快速排序模板
上传时间： 2015-01-04
上传用户：Yukiseop
c++模板小实验
上传时间： 2015-01-06
上传用户：tedo811
一个演示类模板的源代码
上传时间： 2015-01-08
上传用户：cmc_68289287
在C++程序中使用Strategy模板
上传时间： 2015-01-09
上传用户：xymbian
基本的DirectX + MFC 游戏工程模板
上传时间： 2015-01-11
上传用户：agent
用VHDL编写DDR SDRAM Controller的源代码
标签： Controller SDRAM VHDL DDR
上传时间： 2013-12-19
上传用户：hn891122
