This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
cpu+core技术资料下载专区,收录1,418份相关技术文档、开发源码、电路图纸等优质工程师资源,全部免费下载。
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. –...
CPU周期与微指令周期的关系 在串行方式的微程序控制器中: 微指令周期 = 读出微指令的时间 + 执行该条微指令的时间 ...
提出一种综合考虑Agent时间片和执行截止期限要求的CPU时间片组合拍卖遗传算法。该算法定义了问题模型,采用可以去除不具备竞争力标的预选择策略,减少遗传算法的计算复杂度。在遗传算法求解过程中,设计适合
·文件列表: mp3play .......\COPYING .......\CREDITS .......\genre.h .......\http.c ...