While there are many textbooks about the European Union (EU), Clive Archer covers the essential elements of the EU clearly and con- cisely, outlining the key debates and issues it faces today
标签： essential textbooks the European
上传时间： 2014-01-07
上传用户：qilin
While there are many textbooks about the European Union (EU), Clive Archer covers the essential elements of the EU clearly and con- cisely, outlining the key debates and issues it faces today
标签： essential textbooks the European
上传时间： 2013-12-17
上传用户：zl5712176
While there are many textbooks about the European Union (EU), Clive Archer covers the essential elements of the EU clearly and con- cisely, outlining the key debates and issues it faces today
标签： essential textbooks the European
上传时间： 2013-12-09
上传用户：stella2015
While there are many textbooks about the European Union (EU), Clive Archer covers the essential elements of the EU clearly and con- cisely, outlining the key debates and issues it faces today
标签： essential textbooks the European
上传时间： 2014-11-21
上传用户：cursor
Abstract: The DS1875 features a pulse-width modulation (PWM) controller that can be used to control aDC-DC converter. The DC-DC converter can then be used to generate the high bias voltages necessaryfor avalanche photodiodes (APDs). This application note describes the operation of a boost converterthat uses the DS1875. Discussion covers the selection of the inductor and switching frequency, and theselection of components that improve the efficiency of the converter. Test data are presented.
上传时间： 2013-10-26
上传用户：lyson
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
Abstract: Counterfeiting as an international industry covers virtually everything made or manufactured,from auto parts to purses and watches to prescription drugs. In contrast to other counterfeit items, the
上传时间： 2013-12-13
上传用户：阿谭电器工作室
Nios II 系列处理器配置选项:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
上传时间： 2015-01-01
上传用户：mahone
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
上传时间： 2013-11-11
上传用户：y13567890
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.
上传时间： 2013-11-21
上传用户：gtf1207
