This library provides functionality to control any camera that conforms to the 1394-Based Digital Camera Specification (which can be found at http://www.1394ta.org/Download/Technology/Specifications/Camera120.pdf). It utilizes the lowlevel functionality provided by libraw1394 to communicate with the camera.
标签： functionality conforms provides Digital
上传时间： 2013-12-22
上传用户：yuchunhai1990
MD5 Source Code This optimized MD5 implementation conforms to RFC 1321
标签： implementation MD5 optimized conforms
上传时间： 2016-01-23
上传用户：咔乐坞
SHA-1 Source Code This optimized SHA-1 implementation conforms to FIPS 180-1
标签： implementation SHA optimized conforms
上传时间： 2016-01-23
上传用户：xcy122677
AES Source Code This optimized AES implementation conforms to FIPS-197
标签： implementation AES optimized conforms
上传时间： 2013-12-12
上传用户：asasasas
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
SL811开发资料_包含源程序_电路图_芯片资料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
上传时间： 2013-12-22
上传用户：a82531317
