The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上传时间： 2014-11-22
上传用户：xcy122677
keil 使用笔记:在Memory窗口上输入address_type:address才能看到正确地址的变量debug～perfermance analyzer加入要察看的模块名称，然后view～perfermance analyzer window 可以察看各个模块运行时间①Display address_type:address B:Bit address C:Code Memory Bx:Code Bank D D：80H 命令可以查看特殊寄存器 data D I：0 命令可以查看内部RAM数据iData； D X：0 命令可以查看外部RAM数据xData； ②R1 //显示R1 register ~R1 //显示变量R1 R1 = R7 //对寄存器Rx操作R1 = --R7 R1 = 0x20 ③main //显示main()的开始地址d main //显示main()的代码④向RAM.ROM中写数据Enter data_type address_type:address expr,expr.... data_type:int char double float long E char data:0x20 1,2,3,4 //向data区0x20开始的地址写1,2,3,4 变量放在RAM的30H，要把定义放在main前面!另外特别注意，内部RAM通常供C程序存放中间变量等，所以一定要看看编译后的程序中是否存在存储单元冲突的情况，比如如果程序中 使用了别的寄存器组的话，08-1FH单元就不能用了unsigned long data i _at_ 0x30
上传时间： 2013-11-05
上传用户：dongqiangqiang
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
微型计算机课程设计论文—通用微机发声程序的汇编设计 本文讲述了在微型计算机中利用可编程时间间隔定时器的通用发声程序设计，重点讲述了程序的发声原理，节拍的产生，按节拍改变的动画程序原理，并以设计一个简单的乐曲评分程序为引子，分析程序设计的细节。关键字：微机 8253 通用发声程序 动画技术 直接写屏 1. 可编程时间间隔定时器8253在通用个人计算机中，有一个可编程时间间隔定时器8253，它能够根据程序提供的计数值和工作方式,产生各种形状和各种频率的计数/定时脉冲,提供给系统各个部件使用。本设计是利用计算机控制发声的原理,编写演奏乐曲的程序。 在8253/54定时器内部有3个独立工作的计数器:计数器0,计数器1和计数器2,每个计数器都分配有一个断口地址,分别为40H,41H和42H.8253/54内部还有一个公用的控制寄存器,端地址为43H.端口地址输入到8253/54的CS,AL,A0端,分别对3个计数器和控制器寻址. 对8353/54编程时,先要设定控制字,以选择计数器,确定工作方式和计数值的格式.每计数器由三个引脚与外部联系,见教材第320页图9-1.CLK为时钟输入端,GATE为门控信号输入端,OUT为计数/定时信号输入端.每个计数器中包含一个16位计数寄存器,这个计数器时以倒计数的方式计数的,也就是说,从计数初值逐次减1,直到减为0为止. 8253/54的三个计数器是分别编程的,在对任一个计数器编程时,必须首先讲控制字节写入控制寄存器.控制字的作用是告诉8253/54选择哪个计数器工作,要求输出什么样的脉冲波形.另外,对8253/54的初始化工作还包括,向选定的计数器输入一个计数初值,因为这个计数值可以是8为的,也可以是16为的,而8253/5的数据总线是8位的,所以要用两条输出指令来写入初值.下面给出8253/54初始化程序段的一个例子,将计数器2设定为方式3,(关于计数器的工作方式参阅教材第325—330页)计数初值为65536. MOV AL,10110110B ;选择计数器2,按方式3工作,计数值是二进制格式 OUT 43H,AL ; j将控制字送入控制寄存器 MOV AL,0 ;计数初值为0 OUT 42H,AL ;将计数初值的低字节送入计数器2 OUT 42H,AL ;将计数初值的高字节送入计数器2 在IBM PC中8253/54的三个时钟端CLK0,CLK1和CLK2的输入频率都是1.1931817MHZ. PC机上的大多数I/O都是由主板上的8255(或8255A)可编程序外围接口芯片(PPI)管理的.关于8255A的结构和工作原理及应用举例参阅教材第340—373页.教材第364页的”PC/XT机中的扬声器接口电路”一节介绍了扬声器的驱动原理,并给出了通用发声程序.本设计正是基于这个原理,通过编程,控制加到扬声器上的信号的频率,奏出乐曲的.2．发声程序的设计下面是能产生频率为f的通用发声程序:MOV AL, 10110110B ;8253控制字:通道2,先写低字节,后写高字节 ;方式3,二进制计数OUT 43H, AL ;写入控制字MOV DX, 0012H ;被除数高位MOV AX, 35DEH ;被除数低位 DIV ID ;求计数初值n,结果在AX中OUT 42H, AL ;送出低8位MOV AL, AHOUT 42H,AL ;送出高8位IN AL, 61H ;读入8255A端口B的内容MOV AH, AL ;保护B口的原状态OR AL, 03H ;使B口后两位置1,其余位保留OUT 61H,AL ;接通扬声器,使它发声
上传时间： 2013-10-17
上传用户：sunjet
基于USB接口的数据采集模块的设计与实现Design and Implementation of USB-Based Data Acquisition Module路 永 伸(天津科技大学电子信息与自动化学院，天津300222)摘要文中给出基于USB接口的数据采集模块的设计与实现。硬件设计采用以Adpc831与PDIUSBDI2为主的器件进行硬件设计，采用Windriver开发USB驱动，并用Visual C十十6.0对主机软件中硬件接口操作部分进行动态链接库封装。关键词USB 数据采集Adpc831 PDNSBDI2 Windriver动态链接库Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTUSBD12i sused for hardware design. The USB drive is developed场Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries场Visual C++6.0. Keywords USB DataA cquisition Adttc831 PDfUSBD12 Windriver0 引言US B总 线 是新一代接口总线，最初推出的目的是为了统一取代PC机的各类外设接口，迄今经历了1.0,1.1与2.0版本3个标准。在国内基于USB总线的相关设计与开发也得到了快速的发展，很多设计者从各自的应用领域，用不同方案设计出了相应的装置[1,2]。数据采集是工业控制中一个普遍而重要的环节，因此开发基于USB接口的数据采集模块具有很强的现实应用意义。虽然 US B总线标准已经发展到2.0版本，但由于工业控制现场干扰信号的情况比较复杂，高速数据传输的可靠性不容易被保证，并且很多场合对数据采集的实时性要求并不高，开发2.0标准产品的成本又较1.1标准产品高，所以笔者认为，在工业控制领域，目前开发基于USB总线1.1标准实现的数据采集模块的实用意义大于相应2.0标准模块。
上传时间： 2013-10-23
上传用户：q3290766
磁芯电感器的谐波失真分析 摘 要：简述了改进铁氧体软磁材料比损耗系数和磁滞常数ηB，从而降低总谐波失真THD的历史过程，分析了诸多因数对谐波测量的影响，提出了磁心性能的调控方向。 关键词：比损耗系数， 磁滞常数ηB ，直流偏置特性DC-Bias，总谐波失真THD Analysis on THD of the fer rite co res u se d i n i nductancShi Yan Nanjing Finemag Technology Co. Ltd., Nanjing 210033 Abstract: Histrory of decreasing THD by improving the ratio loss coefficient and hysteresis constant of soft magnetic ferrite is briefly narrated. The effect of many factors which affect the harmonic wave testing is analysed. The way of improving the performance of ferrite cores is put forward. Key words: ratio loss coefficient，hysteresis constant，DC-Bias，THD 近年来，变压器生产厂家和软磁铁氧体生产厂家，在电感器和变压器产品的总谐波失真指标控制上，进行了深入的探讨和广泛的合作，逐步弄清了一些似是而非的问题。从工艺技术上采取了不少有效措施，促进了质量问题的迅速解决。本文将就此热门话题作一些粗浅探讨。 一、 历史回顾 总谐波失真（Total harmonic distortion） ，简称THD，并不是什么新的概念，早在几十年前的载波通信技术中就已有严格要求<1>。1978年邮电部公布的标准YD/Z17－78“载波用铁氧体罐形磁心”中，规定了高μQ材料制作的无中心柱配对罐形磁心详细的测试电路和方法。如图一电路所示，利用LC组成的150KHz低通滤波器在高电平输入的情况下测量磁心产生的非线性失真。这种相对比较的实用方法，专用于无中心柱配对罐形磁心的谐波衰耗测试。 这种磁心主要用于载波电报、电话设备的遥测振荡器和线路放大器系统，其非线性失真有很严格的要求。 图中 ZD —— QF867 型阻容式载频振荡器，输出阻抗 150Ω， Ld47 —— 47KHz 低通滤波器，阻抗 150Ω，阻带衰耗大于61dB， Lg88 ——并联高低通滤波器，阻抗 150Ω，三次谐波衰耗大于61dB Ld88 ——并联高低通滤波器，阻抗 150Ω，三次谐波衰耗大于61dB FD —— 30～50KHz 放大器， 阻抗 150Ω， 增益不小于 43 dB，三次谐波衰耗b3(0)≥91 dB, DP —— Qp373 选频电平表，输入高阻抗， L ——被测无心罐形磁心及线圈， C ——聚苯乙烯薄膜电容器CMO-100V-707APF±0.5%,二只。 测量时，所配用线圈应用丝包铜电磁线SQJ9×0.12(JB661-75)在直径为16.1mm的线架上绕制 120 匝， （线架为一格） ， 其空心电感值为 318μH（误差1％） 被测磁心配对安装好后，先调节振荡器频率为 36.6～40KHz， 使输出电平值为+17.4 dB， 即选频表在 22′端子测得的主波电平 （P2）为+17.4 dB，然后在33′端子处测得输出的三次谐波电平（P3）， 则三次谐波衰耗值为：b3(+2)= P2+S+ P3 式中：S 为放大器增益dB 从以往的资料引证， 就可以发现谐波失真的测量是一项很精细的工作，其中测量系统的高、低通滤波器，信号源和放大器本身的三次谐波衰耗控制很严，阻抗必须匹配，薄膜电容器的非线性也有相应要求。滤波器的电感全由不带任何磁介质的大空心线圈绕成，以保证本身的“洁净” ，不至于造成对磁心分选的误判。 为了满足多路通信整机的小型化和稳定性要求， 必须生产低损耗高稳定磁心。上世纪 70 年代初，1409 所和四机部、邮电部各厂，从工艺上改变了推板空气窑烧结，出窑后经真空罐冷却的落后方式，改用真空炉，并控制烧结、冷却气氛。技术上采用共沉淀法攻关试制出了μQ乘积 60 万和 100 万的低损耗高稳定材料，在此基础上，还实现了高μ7000～10000材料的突破，从而大大缩短了与国外企业的技术差异。当时正处于通信技术由FDM（频率划分调制）向PCM（脉冲编码调制） 转换时期， 日本人明石雅夫发表了μQ乘积125 万为 0.8×10 ，100KHz）的超优铁氧体材料<3>，其磁滞系数降为优铁
上传时间： 2013-12-15
上传用户：天空说我在
Java Clock is a FREE Java applet used to display a clock on your Web pages. You can display either analog or digital clock. The full source code of this applet is also available (visit my home page to download it). You may use this applet on your Web pages WITHOUT paying me fee or royalty as long as credit is given (a link to my home page is enough).
标签： display Java applet either
上传时间： 2014-01-12
上传用户：woshiayin
介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
标签： architecture introducin peripheral improves
上传时间： 2015-03-15
上传用户：ccclll
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane wave source is inserted at one end. First released 12 April 1999. Version 1.03 released 2 December 1999.
标签： demonstrating stripped-down implementing minimalist
上传时间： 2013-12-21
上传用户：无聊来刷下
VC技术内幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In addition to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.
标签： Microsoft continued Internet English
上传时间： 2013-12-08
上传用户：lepoke
