搜索：clocked
找到约 11 项符合「clocked」的查询结果
结果 11
https://www.eeworm.com/dl/648/261407.html
单片机开发
/*SPI规范：Data is always clocked into the device on the rising edge of SCK a-*/ /* nd clocked out of
/*SPI规范：Data is always clocked into the device on the rising edge of SCK a-*/
/* nd clocked out of the device on the falling edge of SCK.All instruction-*/
/* s,addresses and data are transferred with the most significant bit(MSB) */
/* first.
https://www.eeworm.com/dl/516/403312.html
DSP编程
The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or the USB DP
The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or the
USB DPLL. Since the APLL is inherently more noise tolerant and has less long-term jitter than the DPLL,
it is recommended that you switch to it for any USB operations.
https://www.eeworm.com/dl/855759.html
技术资料
AST2400
The embedded ARM9 and DDR3 is clocked at 400MHz to meet the increasing performance requirements.
https://www.eeworm.com/dl/915008.html
技术资料
介绍CY7C441 CY7C443 CY7451 CY7C453定时先进先出存储器系列的基本性能和工作
This application note explains the basic operations and features of Cypress clocked FIFO memories
https://www.eeworm.com/dl/918960.html
技术资料
介绍Cypress的定时 FIFO存储器的基本工作和特性
This application note explains the basic operations and features of Cypress clocked FIFO memories. C
https://www.eeworm.com/dl/920151.html
技术资料
4042 CMOS 四时钟控制D锁存器
The CD4042BM/CD4042BC quad clocked ``D'' latch is amonolithic complementary MOS (CMOS) integrate
https://www.eeworm.com/dl/663/292193.html
VHDL/FPGA/Verilog
vhdl编写
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
E ...
https://www.eeworm.com/dl/648/282976.html
单片机开发
// This program measures the voltage on an external ADC input and prints the // result to a termin
// This program measures the voltage on an external ADC input and prints the
// result to a terminal window via the UART.
//
// The system is clocked using the internal 24.5MHz oscillator.
// Results are printed to the UART from a loop with the rate set by a delay
// based on ...
https://www.eeworm.com/dl/663/268989.html
VHDL/FPGA/Verilog
计数器 锁存器 12位寄存器 带load
计数器
锁存器
12位寄存器
带load，clr等功能的寄存器
双向脚（clocked bidirectional pin）
一个简单的状态机
一个同步状态机
用状态机设计的交通灯控制器
数据接口
一个简单的UART
测试向量（Test Bench）举例：
加法器源程序 相应加法器的测试向量test bench） ...
https://www.eeworm.com/dl/892605.html
技术资料
具有预计算功能的新型绝热数值比较器设计
摘 要：该文通过对钟控传输门绝热逻辑(Clocked Transmission Gate Adiabatic Logic，CTGAL)电路和数值比较器电路工作原理及结构的研究，提出了一种基于CTGAL 电路的具有预计算功能的新型绝热数值比较器设计方案。该方案具有冗余抑制作用，将其与利用PAL-2N 电路设计的低功耗绝热数值比较器相比，功耗节 ...