使用奇异值分解算法的prony算法-single value decomposition based prony algorithm
标签： prony decomposition algorithm single
上传时间： 2014-01-26
上传用户：大三三
FM1702的例子程序 Chip type : ATmega16L Program type : Application Clock frequency : 7.372800 MHz Memory model : Small External SRAM size : 0 Data Stack size : 256
标签： type Application frequency 7.372800
上传时间： 2016-10-08
上传用户：chfanjiang
Design of Image Collection System Based on High-speed PCI Bus基于PCI总线的高速图像采集系统设计
标签： Collection High-speed PCI Design
上传时间： 2013-12-24
上传用户：上善若水
Design of High Speed Multichannel Data Gathering System Based on FPGA基于FPGA的高速多通道数据采集系统的设计
标签： FPGA Multichannel Gathering Design
上传时间： 2016-10-10
上传用户：chenbhdt
Export a vertices/faces patch to an STL triangular mesh.This is based heavily on Bill McDonald s previous work, simply enabling his output functions for a different form of input.
标签： triangular vertices McDonald heavily
上传时间： 2014-01-12
上传用户：lindor
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
标签： simulation Verilog writing clock
上传时间： 2016-10-12
上传用户：王者A
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.
标签： Clock_Dithering_Verilog u_dither Verilog Clock
上传时间： 2013-12-09
上传用户：
RTL8091 10 based ethernet interface programming application note
标签： application programming interface ethernet
上传时间： 2016-10-14
上传用户：fandeshun
CIRRUS LAN(tm) CS8900 VxWORKS MUX-Based ENHANCED NETWORK DRIVER (END)
标签： MUX-Based ENHANCED VxWORKS NETWORK
上传时间： 2013-12-05
上传用户：stewart·
CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
标签： polynomial Features Executes clock
上传时间： 2013-12-18
上传用户：Ants
