This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal.
This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal....
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This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal....
Application Note Abstract The unique configuration of the PSoC® switched capacitor blocks allows...
The configuration file reading samples for ARM project development. Including the sample .conf files...
SQLite is a software library that implements a self-contained, serverless, zero-configuration, trans...
MSP-FET430P120 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10...
many application on kit SP-3: VGA, digital clock, counter, interface PS2.......
NIST is a script to update the Linux clock with NTP servers....
三国 Manifest-Version: 1.0 MicroEdition-Configuration: CLDC-1.0 MIDlet-Data-Size: 15000 MIDlet-Descrip...
Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (fa...
Ezusb (cypress) USB 2.0 family firmware for data transfer including 4 endpoints configuration and cr...