虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

bottom-up

  • PCB抄板密技

    第一步,拿到一块PCB,首先在纸上记录好所有元气件的型号,参数,以及位置,尤其是二极管,三机管的方向,IC缺口的方向。最好用数码相机拍两张元气件位置的照片。第二步,拆掉所有器件,并且将PAD孔里的锡去掉。用酒精将PCB清洗干净,然后放入扫描仪内,启动POHTOSHOP,用彩色方式将丝印面扫入,并打印出来备用。第三步,用水纱纸将TOP LAYER 和BOTTOM LAYER两层轻微打磨,打磨到铜膜发亮,放入扫描仪,启动PHOTOSHOP,用彩色方式将两层分别扫入。注意,PCB在扫描仪内摆放一定要横平树直,否则扫描的图象就无法使用。第四步,调整画布的对比度,明暗度,使有铜膜的部分和没有铜膜的部分对比强烈,然后将次图转为黑白色,检查线条是否清晰,如果不清晰,则重复本步骤。如果清晰,将图存为黑白BMP格式文件TOP.BMP和BOT.BMP。第五步,将两个BMP格式的文件分别转为PROTEL格式文件,在PROTEL中调入两层,如过两层的PAD和VIA的位置基本重合,表明前几个步骤做的很好,如果有偏差,则重复第三步。第六,将TOP。BMP转化为TOP。PCB,注意要转化到SILK层,就是黄色的那层,然后你在TOP层描线就是了,并且根据第二步的图纸放置器件。画完后将SILK层删掉。 第七步,将BOT。BMP转化为BOT。PCB,注意要转化到SILK层,就是黄色的那层,然后你在BOT层描线就是了。画完后将SILK层删掉。第八步,在PROTEL中将TOP。PCB和BOT。PCB调入,合为一个图就OK了。第九步,用激光打印机将TOP LAYER, BOTTOM LAYER分别打印到透明胶片上(1:1的比例),把胶片放到那块PCB上,比较一下是否有误,如果没错,你就大功告成了。

    标签: PCB 抄板

    上传时间: 2013-11-24

    上传用户:ynzfm

  • pcb layout design(台湾硬件工程师15年经验

    PCB LAYOUT 術語解釋(TERMS)1. COMPONENT SIDE(零件面、正面)︰大多數零件放置之面。2. SOLDER SIDE(焊錫面、反面)。3. SOLDER MASK(止焊膜面)︰通常指Solder Mask Open 之意。4. TOP PAD︰在零件面上所設計之零件腳PAD,不管是否鑽孔、電鍍。5. BOTTOM PAD:在銲錫面上所設計之零件腳PAD,不管是否鑽孔、電鍍。6. POSITIVE LAYER:單、雙層板之各層線路;多層板之上、下兩層線路及內層走線皆屬之。7. NEGATIVE LAYER:通常指多層板之電源層。8. INNER PAD:多層板之POSITIVE LAYER 內層PAD。9. ANTI-PAD:多層板之NEGATIVE LAYER 上所使用之絕緣範圍,不與零件腳相接。10. THERMAL PAD:多層板內NEGATIVE LAYER 上必須零件腳時所使用之PAD,一般稱為散熱孔或導通孔。11. PAD (銲墊):除了SMD PAD 外,其他PAD 之TOP PAD、BOTTOM PAD 及INNER PAD 之形狀大小皆應相同。12. Moat : 不同信號的 Power& GND plane 之間的分隔線13. Grid : 佈線時的走線格點2. Test Point : ATE 測試點供工廠ICT 測試治具使用ICT 測試點 LAYOUT 注意事項:PCB 的每條TRACE 都要有一個作為測試用之TEST PAD(測試點),其原則如下:1. 一般測試點大小均為30-35mil,元件分布較密時,測試點最小可至30mil.測試點與元件PAD 的距離最小為40mil。2. 測試點與測試點間的間距最小為50-75mil,一般使用75mil。密度高時可使用50mil,3. 測試點必須均勻分佈於PCB 上,避免測試時造成板面受力不均。4. 多層板必須透過貫穿孔(VIA)將測試點留於錫爐著錫面上(Solder Side)。5. 測試點必需放至於Bottom Layer6. 輸出test point report(.asc 檔案powerpcb v3.5)供廠商分析可測率7. 測試點設置處:Setup􀃆pads􀃆stacks

    标签: layout design pcb 硬件工程师

    上传时间: 2013-11-17

    上传用户:cjf0304

  • pci e PCB设计规范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    标签: pci PCB 设计规范

    上传时间: 2014-01-24

    上传用户:s363994250

  • 8259 VHDL代码

    a8259 可编程中断控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface  in 8088 and 8086  based microcomputer systems. The device is known as a programmable interrupt controller.  The a8259 receives and prioritizes up to 8 interrupts,  and in the cascade mode, this can be expanded up to  64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.

    标签: 8259 VHDL 代码

    上传时间: 2015-01-02

    上传用户:panpanpan

  • LT5514三阶互调的精确测量

      Accurate measurement of the third order intercept pointfor low distortion IC products such as the LT5514 requirescertain precautions to be observed in the test setup andtesting procedure. The LT5514 linearity performance ishigh enough to push the test equipment and test set-up totheir limits. A method for accurate measurement of thirdorder intermodulation products, IM3, with standard testequipment is outlined below.It is also important to correctly interpret the LT5514specification with respect to ROUT, and the impact ofdemo-board transmission-line termination loss whenevaluating the linearity performance, as explained in theLT5514 Datasheet and in Note 1 of this document.

    标签: 5514 LT 三阶互调 精确测量

    上传时间: 2013-11-14

    上传用户:l254587896

  • superpro 3000u 驱动及编程器软件下载

    superpro 3000u 驱动 PIC16C65B@QFP44 [SA245] PIC16C65B:          Part number QFP44:              Package in QFP44 SA245:              Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT:        Part number FBGA48:             Package in FBGA48 SA642:              Adapter purchase number (Top board with socket) B026:               Adapter purchase number (Bottom board, exchangable for different parts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA:           Part number PLCC68:             Package in PLCC68 universal adapter:  this adapter is valid for all parts in this package PEP:                The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T:              Adapter purchase number (Universal for all parts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B:            Part number FBGA64:                  Package in FBGA64 special adapter:         this adapter is valid for this

    标签: superpro 3000u 驱动 编程器软件

    上传时间: 2014-03-27

    上传用户:ippler8

  • Cimatron E 7.0教程

    Cimatron E 7.0教程 使用Cimatron E 起草应用,建立部分或者组装图图表是可能的,由2D 风景组成。在画的每一个内有一条或更多床单,起草的符号和注释可能被增加并且编辑。 这些画图表包含象 起草标准那样的具体的特性,意见归因于,框架,模板等等。在各种各样的起草的概念将的这个练习过程中沿着边讨论Cimatron E的动态的能力。 1、打开一份起草的资料 Open up the Drafting application within Cimatron E. 2、现在起草应用的Cimatron 打开 资料在Cimatron E里使用起草被叫为一张画。 有一条床单的一张画被创造一份起草的资料自动创 造。 3、建立床单 一条床单包含一个一个模型,部分或者会议的2D 意见的布局。 除2D之外几何学建立使用 sketcher,起草符号,注释能被增加给床单。 无限的床单的数量能被归入一张画允许一象要求 的那样安排许多意见。

    标签: Cimatron 7.0 教程

    上传时间: 2013-10-21

    上传用户:

  • This Unix C code monitors a web server every few minutes by trying to retrieve its home page. It sen

    This Unix C code monitors a web server every few minutes by trying to retrieve its home page. It sends you email when it can t connect, and every so often while the server is still down. It sends a final message when it comes back up. If you have email paging, just direct the email to your pager address.

    标签: monitors retrieve minutes server

    上传时间: 2015-01-11

    上传用户:pompey

  • This hands-on, one-stop guide delivers the focused, streamlined direction you need to get your Web s

    This hands-on, one-stop guide delivers the focused, streamlined direction you need to get your Web solutions up and running quickly. Zero in on key ASP.NET configuration details and techniques using quick-reference tables, lists, coding and more.

    标签: streamlined direction hands-on delivers

    上传时间: 2015-01-11

    上传用户:Thuan

  • ATmega8 taillight circuitA more complex C program that implements different flashing patterns under

    ATmega8 taillight circuitA more complex C program that implements different flashing patterns under the control of both the push buttons and potentiometer. Use your imagination to come up with some novel ideas here. Remember however that more marks are to be awarded for the quality of the code than for the novelness of the patterns.

    标签: implements taillight different circuitA

    上传时间: 2013-11-27

    上传用户:zhuimenghuadie