keil 使用笔记:在Memory窗口上输入address_type:address才能看到正确地址的变量debug～perfermance analyzer加入要察看的模块名称，然后view～perfermance analyzer window 可以察看各个模块运行时间①Display address_type:address B:Bit address C:Code Memory Bx:Code Bank D D：80H 命令可以查看特殊寄存器 data D I：0 命令可以查看内部RAM数据iData； D X：0 命令可以查看外部RAM数据xData； ②R1 //显示R1 register ~R1 //显示变量R1 R1 = R7 //对寄存器Rx操作R1 = --R7 R1 = 0x20 ③main //显示main()的开始地址d main //显示main()的代码④向RAM.ROM中写数据Enter data_type address_type:address expr,expr.... data_type:int char double float long E char data:0x20 1,2,3,4 //向data区0x20开始的地址写1,2,3,4 变量放在RAM的30H，要把定义放在main前面!另外特别注意，内部RAM通常供C程序存放中间变量等，所以一定要看看编译后的程序中是否存在存储单元冲突的情况，比如如果程序中 使用了别的寄存器组的话，08-1FH单元就不能用了unsigned long data i _at_ 0x30
上传时间： 2013-11-05
上传用户：dongqiangqiang
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
load initial_track s; % y:initial data,s:data with noiseT=0.1; % yp denotes the sample value of position% yv denotes the sample value of velocity% Y=[yp(n);yv(n)];% error deviation caused by the random acceleration % known dataY=zeros(2,200);Y0=[0;1];Y(:,1)=Y0;A=[1 T 0 1]; B=[1/2*(T)^2 T]';H=[1 0]; C0=[0 0 0 1];C=[C0 zeros(2,2*199)];Q=(0.25)^2; R=(0.25)^2;
上传时间： 2014-12-28
上传用户：asaqq
附件有二个文当，都是dxp2004教程 ，第一部份DXP2004的相关快捷键，以及中英文对照的意思。第二部份细致的讲解的如何使用DXP2004。 dxp2004教程第一部份： 目录 1 快捷键 2 常用元件及封装 7 创建自己的集成库 12 板层介绍 14 过孔 15 生成BOM清单 16 顶层原理图: 16 生成PCB 17 包地 18 电路板设计规则 18 PCB设计注意事项 20 画板心得 22 DRC 规则英文对照 22 一、Error Reporting 中英文对照 22 A ： Violations Associated with Buses 有关总线电气错误的各类型（共 12 项） 22 B ：Violations Associated Components 有关元件符号电气错误（共 20 项） 22 C ： violations associated with document 相关的文档电气错误（共 10 项） 23 D ： violations associated with nets 有关网络电气错误（共 19 项） 23 E ： Violations associated with others 有关原理图的各种类型的错误 (3 项 ) 24 二、 Comparator 规则比较 24 A ： Differences associated with components 原理图和 PCB 上有关的不同 ( 共 16 项 ) 24 B ： Differences associated with nets 原理图和 PCB 上有关网络不同（共 6 项） 25 C ： Differences associated with parameters 原理图和 PCB 上有关的参数不同（共 3 项） 25 Violations Associated withBuses栏 —总线电气错误类型 25 Violations Associated with Components栏 ——元件电气错误类型 26 Violations Associated with documents栏 —文档电气连接错误类型 27 Violations Associated with Nets栏 ——网络电气连接错误类型 27 Violations Associated with Parameters栏 ——参数错误类型 28 dxp2004教程第二部份 路设计自动化（ Electronic Design Automation ） EDA 指的就是将电路设计中各种工作交由计算机来协助完成。如电路图（ Schematic ）的绘制，印刷电路板（ PCB ）文件的制作执行电路仿真（ Simulation ）等设计工作。随着电子工业的发展，大规模、超大规模集成电路的使用是电路板走线愈加精密和复杂。电子线路 CAD 软件产生了， Protel 是突出的代表，它操作简单、易学易用、功能强大。 1.1 Protel 的产生及发展 1985 年 诞生 dos 版 Protel 1991 年 Protel for Widows 1998 年 Protel98 这个 32 位产品是第一个包含 5 个核心模块的 EDA 工具 1999 年 Protel99 既有原理图的逻辑功能验证的混合信号仿真，又有了 PCB 信号完整性 分析的板级仿真，构成从电路设计到真实板分析的完整体系。 2000 年 Protel99se 性能进一步提高，可以对设计过程有更大控制力。 2002 年 Protel DXP 集成了更多工具，使用方便，功能更强大。 1.2 Protel DXP 主要特点 1 、通过设计档包的方式，将原理图编辑、电路仿真、 PCB 设计及打印这些功能有机地结合在一起，提供了一个集成开发环境。 2 、提供了混合电路仿真功能，为设计实验原理图电路中某些功能模块的正确与否提供了方便。 3 、提供了丰富的原理图组件库和 PCB 封装库，并且为设计新的器件提供了封装向导程序，简化了封装设计过程。 4 、提供了层次原理图设计方法，支持“自上向下”的设计思想，使大型电路设计的工作组开发方式成为可能。 5 、提供了强大的查错功能。原理图中的 ERC （电气法则检查）工具和 PCB 的 DRC （设计规则检查）工具能帮助设计者更快地查出和改正错误。 6 、全面兼容 Protel 系列以前版本的设计文件，并提供了 OrCAD 格式文件的转换功能。 7 、提供了全新的 FPGA 设计的功能，这好似以前的版本所没有提供的功能。
上传时间： 2015-01-01
上传用户：zhyfjj
目录 目录 1 快捷键 2 常用元件及封装 7 创建自己的集成库 12 板层介绍 14 过孔 15 生成BOM清单 16 顶层原理图: 16 生成PCB 17 包地 18 电路板设计规则 18 PCB设计注意事项 20 画板心得 22 DRC 规则英文对照 22 一、Error Reporting 中英文对照 22 A ： Violations Associated with Buses 有关总线电气错误的各类型（共 12 项） 22 B ：Violations Associated Components 有关元件符号电气错误（共 20 项） 22 C ： violations associated with document 相关的文档电气错误（共 10 项） 23 D ： violations associated with nets 有关网络电气错误（共 19 项） 23 E ： Violations associated with others 有关原理图的各种类型的错误 (3 项 ) 24 二、 Comparator 规则比较 24 A ： Differences associated with components 原理图和 PCB 上有关的不同 ( 共 16 项 ) 24 B ： Differences associated with nets 原理图和 PCB 上有关网络不同（共 6 项） 25 C ： Differences associated with parameters 原理图和 PCB 上有关的参数不同（共 3 项） 25 Violations Associated withBuses栏 —总线电气错误类型 25 Violations Associated with Components栏 ——元件电气错误类型 26 Violations Associated with documents栏 —文档电气连接错误类型 27 Violations Associated with Nets栏 ——网络电气连接错误类型 27 Violations Associated with Parameters栏 ——参数错误类型 28
上传时间： 2013-11-21
上传用户：旭521
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable
标签： continous IDCT-M accept medium
上传时间： 2015-07-07
上传用户：1583060504
/*** *** *** *** *** *** *** *** *** *** *** *** **/ //**此映射表用来映射LED模块不译码时，显示的字符和必须输入的数据的关系 //**每段和对应比特位的关系见示意图 // g // --- --- // b | a |f | | <---显示0时点亮的段为gfedcb // --- // c | |e | | 那么写入数据为0x7e // --- --- // d // bit: 7 6 5 4 3 2 1 0 // 段位： g f e d c b a
上传时间： 2013-11-25
上传用户：
Thinking in Java, 3rd ed. Revision 4.0 Preface Introduction 1: Introduction to Objects 2: Everything is an Object 3: Controlling Program Flow 4: Initialization & Cleanup 5: Hiding the Implementation 6: Reusing Classes 7: Polymorphism 8: Interfaces & Inner Classes 9: Error Handling with Exceptions 10: Detecting Types 11: Collections of Objects 12: The Java I/O System 13: Concurrency 14: Creating Windows & Applets 15: Discovering Problems 16: Analysis and Design A: Passing & Returning Objects B: Java Programming Guidelines C: Supplements D: Resources Index
标签： Introduction Thinking Revision Preface
上传时间： 2014-07-13
上传用户：netwolf
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
标签： conversion Includes parallel stuffing
上传时间： 2017-03-11
上传用户：hn891122
SCSI-3 Multimedia Commands X3T10 1228D 4.1.1. CD address reporting formats (MSF bit) Several CD commands can report addresses either in logical block address or in MSF format (see Error! Reference source not found.). The READ HEADER, READ SUB-CHANNEL, and READ TOC/PMA/ATIP commands have this feature.
标签： Multimedia reporting Commands Several
上传时间： 2014-01-01
上传用户：lhc9102
