We describe and demonstrate an algorithm that takes as input an unorganized set of points fx1И
We describe and demonstrate an algorithm that takes as input an unorganized set of points fx1И...
Wide-input技术资料
📦 资源总数：826
💻 源代码：182500
🔌 电路图：2
📚 Wide-input全部资料 (826个)
Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset -
Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset -...
WIDE工作流系统是意大利
WIDE工作流系统是意大利，瑞士等几国研究的工作流系统，文档介绍其原理和流程...
J2ME CANVAS INPUT IN CHINESE
J2ME CANVAS INPUT IN CHINESE...
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs ...
数值计算牛顿迭代法的matlab源程序 说明如下： ％fun----input,the part as the form of f(x) in the equation f(x)=0 ％ ini
数值计算牛顿迭代法的matlab源程序 说明如下： ％fun----input,the part as the form of f(x) in the equation f(x)=0 ％ ini...
数值分析高斯——列主元消去法主程序 说明如下： ％ a----input,matrix of coefficient ％ b----input,right vector ％ sol----o
数值分析高斯——列主元消去法主程序 说明如下： ％ a----input,matrix of coefficient ％ b----input,right vector ％ sol----o...
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input...
verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y
verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y...
verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient
verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient...