viterbi 约束长度为7的仿真
viterbi 约束长度为7的仿真,适用于DAB等卷积编码译码的仿真...
viterbi 约束长度为7的仿真,适用于DAB等卷积编码译码的仿真...
viterbi译码算法的matlab源代码...
viterbi译码算法的matlab源代码...
实现了卷积码的viterbi译码,软判决和硬判决均可实现,是从英文教学书上抄下来的。...
GAR算法ppt An Intelligent Network Routing Algorithm by a Genetic Algorithm...
Analytical constant-modulus algorithm, to separate linear combinations of CM sourcesThe algorithm i...
THis is part algorithm which is data base classification algorithm implemented in java...
Algorithm: Heuristics depth-first search Breadth-first search Algorithm for Tree Algorthm for ...
本文以某型号接收机的应用为背景,主要论述了如何实现基于FPGA的参数化的Viterbi译码器的知识产权(IP)核。文中详细论述了译码器的内部结构、VerilogHDL(硬件描述语言)实现、仿真测试等。...
论文格式,内含Viterbi编解码器的完整vhdl代码,文件为.nh格式...