SystemVerilog for Design
·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). Th...
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·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). Th...
Intel Haswell Platform Design Guideline for Desk Top
Xilinx ISE Design Suite是利用新技术来降低总设计成本的电子设计套件软件,并且实现了比任何其它 PLD 解决方案更高的性能。
Good Code Document,this is a C++ design help document,is good ,help design program
DBDesigner 4 is a database design system that integrates database design, modelling, creation and maintenance into a sin...
Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for opt...
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHD...
本论文依据IEEE802.16a物理层对RS-CC码的参数要求,研究了RS-CC码的高速编、译码的VLSI硬件算法,同时对FPGA开发技术进行了研究,以VerilogHDL为描述语言,在Xilinx公司的FPGA上实现了高速的RS-CC...
· 摘要: AVS-P7(即AVS-M)是AVS系列标准中的第七部分移动视频编码标准.提出一种基于AVS-P7运动补偿单元的VLSI结构,采用改进的片上RAM读写机制和插值计算单元结构,以较少内存访问次数和较低的硬件代...
VLSi KL partitioning Algorithm based programme for 100 nodes. It s dynamic progremme so by changing the MAX value we ca...