CAM is useful vhdl code to understand its architecture which helps to write any code
标签： code architecture understand useful
上传时间： 2017-09-05
上传用户：天涯
Workshop vhdl code from Esperan
标签： Workshop Esperan vhdl code
上传时间： 2013-12-05
上传用户：541657925
Usart model in vhdl code
上传时间： 2013-12-17
上传用户：wxhwjf
Vhdl code for seven segment, in english made by university student
标签： sseg
上传时间： 2017-04-23
上传用户：friede17
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
Analog-to-Digital Converter，VHDL code
标签： Analog-to-Digital Converter
上传时间： 2014-11-30
上传用户：cazjing
是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code
上传时间： 2016-10-24
上传用户：maizezhen
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2014-01-02
上传用户：二驱蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2017-07-05
上传用户：zhoujunzhen
這是Originl公司出的8051 VHDL source code.
上传时间： 2014-01-01
上传用户：ljt101007
