A Top-Down Verilog-A Design on the digital phase-lockedmloop
A Top-Down Verilog-A Design on the digital phase-lockedmloop
TIMER-A,专为精确时间控制而设计的定时器模块,广泛应用于嵌入式系统、工业自动化及消费电子等领域。其灵活的配置选项与高精度特性,使得在实现复杂时序逻辑控制方面表现出色。无论是初学者还是资深开发者,都能在这里找到丰富的学习资料和技术文档,12423个精选资源助力您快速掌握TIMER-A的应用技巧,...
A Top-Down Verilog-A Design on the digital phase-lockedmloop
A project by word about a fee collection system on highway
its a ofdma simulink model. with a modulation scheme on 8psk
a bout union_find set , which is a very useful data structrue.
a genetic algorithm to find the maximum of a polynomial function
this is a sample of a java bot. use to educate..
A code that show the count back to a date determinate.
Program that demonstrates a socket connection in a mobile phone scenario.
Displaying A Picture On A 128x64 Graphical LCD Using PIC 16f877
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to ...