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Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

2017-07-19 109 Synthesis+Tool

· 作者：Premal Buch Amit Narayan A. Richard Newton A. Sangiovanni-Vincentelli 出版社：Department of Electrical Engineering...

2024-11-15 8 Synthesis+Tool

资料->【E】光盘论文->【E5】英文书籍->A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits (英).pdf

2024-11-27 6 Synthesis+Tool

资料->【C】嵌入系统->【C2】IC设计与FPGA->【3】其它->【Verilog HDL、VHDL、硬件描述语言】->(Kluwer) Verilog Quickstart--Practical Guide to Simulation...

2023-05-19 7 Synthesis+Tool

TCL(tool command language)源代码，在IC卡和其他应用中的常用工具。

2013-12-09 159 Synthesis+Tool

2014-01-20 117 Synthesis+Tool

2013-12-25 96 Synthesis+Tool

2015-12-17 77 Synthesis+Tool

2014-01-19 122 Synthesis+Tool

2014-09-03 49 Synthesis+Tool

Synthesis+Tool