源码文件
/* * sha1prog_rom generated by KCAsm at Sat May 26 15:39:09 EDT 2007 */ module sha1prog_rom(address, instruction, clk); input […
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源码文件
/* * test3_rom generated by KCAsm at Sat May 26 15:39:10 EDT 2007 */ module test3_rom(address, instruction, clk); input [9:0] a…
源码文件
/* * fg_ctrl_rom generated by KCAsm at Sat May 26 15:39:06 EDT 2007 */ module fg_ctrl_rom(address, instruction, clk); input [9:…
源码文件
/* * pb3_test_rom generated by KCAsm at Sat May 26 15:39:08 EDT 2007 */ module pb3_test_rom(address, instruction, clk); input […
源码文件
/* * int_test_rom generated by KCAsm at Sat May 26 15:39:06 EDT 2007 */ module int_test_rom(address, instruction, clk); input […
源码文件
/* * uclock_rom generated by KCAsm at Sat May 26 15:39:11 EDT 2007 */ module uclock_rom(address, instruction, clk); input [9:0]…
源码文件
//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2004 Xilinx, Inc. // All Right…
源码文件
module int_test(address, instruction, clk); input [7:0] address; output [15:0] instruction; input clk; RAMB4_S16 ram_256_x_16( .D…
源码文件
This directory contains report files after synthesis run.
源码文件
Release 7.1i - xst H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.0…