div_clk_381hz.syr

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Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Reading design: div_clk_381hz.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "div_clk_381hz.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "div_clk_381hz"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : div_clk_381hz
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : div_clk_381hz.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "div_clk_381hz.v"
Module <div_clk_381hz> compiled
No errors in compilation
Analysis of file <"div_clk_381hz.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <div_clk_381hz>.
Module <div_clk_381hz> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <div_clk_381hz>.
    Related source file is "div_clk_381hz.v".
    Found 17-bit up counter for signal <clk>.
    Summary:
	inferred   1 Counter(s).
Unit <div_clk_381hz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 17-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <div_clk_381hz> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block div_clk_381hz, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : div_clk_381hz.ngr
Top Level Output File Name         : div_clk_381hz
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 2

Macro Statistics :
# Registers                        : 1
#      17-bit register             : 1
# Adders/Subtractors               : 1
#      17-bit adder                : 1

Cell Usage :
# BELS                             : 51
#      GND                         : 1
#      INV                         : 1
#      LUT1_L                      : 16
#      MUXCY                       : 16
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 17
#      FD                          : 17
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                       9  out of   3584     0%  
 Number of Slice Flip Flops:            17  out of   7168     0%  
 Number of 4 input LUTs:                16  out of   7168     0%  
 Number of bonded IOBs:                  2  out of    141     1%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_50Mhz                        | BUFGP                  | 17    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.255ns (Maximum Frequency: 235.026MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock_50Mhz'
  Clock period: 4.255ns (frequency: 235.026MHz)
  Total number of paths / destination ports: 153 / 17
-------------------------------------------------------------------------
Delay:               4.255ns (Levels of Logic = 17)
  Source:            clk_1 (FF)
  Destination:       clk_16 (FF)
  Source Clock:      clock_50Mhz rising
  Destination Clock: clock_50Mhz rising

  Data Path: clk_1 to clk_16
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.976  clk_1 (clk_1)
     LUT1_L:I0->LO         1   0.479   0.000  clk_1_rt (clk_1_rt)
     MUXCY:S->O            1   0.435   0.000  div_clk_381hz_clk__n0000<1>cy (div_clk_381hz_clk__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<2>cy (div_clk_381hz_clk__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<3>cy (div_clk_381hz_clk__n0000<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<4>cy (div_clk_381hz_clk__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<5>cy (div_clk_381hz_clk__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<6>cy (div_clk_381hz_clk__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<7>cy (div_clk_381hz_clk__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<8>cy (div_clk_381hz_clk__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<9>cy (div_clk_381hz_clk__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<10>cy (div_clk_381hz_clk__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<11>cy (div_clk_381hz_clk__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<12>cy (div_clk_381hz_clk__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<13>cy (div_clk_381hz_clk__n0000<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  div_clk_381hz_clk__n0000<14>cy (div_clk_381hz_clk__n0000<14>_cyo)
     MUXCY:CI->O           0   0.056   0.000  div_clk_381hz_clk__n0000<15>cy (div_clk_381hz_clk__n0000<15>_cyo)
     XORCY:CI->O           1   0.786   0.000  div_clk_381hz_clk__n0000<16>_xor (clk__n0000<16>)
     FD:D                      0.176          clk_16
    ----------------------------------------
    Total                      4.255ns (3.279ns logic, 0.976ns route)
                                       (77.1% logic, 22.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock_50Mhz'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.280ns (Levels of Logic = 1)
  Source:            clk_16 (FF)
  Destination:       clk17b (PAD)
  Source Clock:      clock_50Mhz rising

  Data Path: clk_16 to clk17b
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   0.745  clk_16 (clk_16)
     OBUF:I->O                 4.909          clk17b_OBUF (clk17b)
    ----------------------------------------
    Total                      6.280ns (5.535ns logic, 0.745ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
CPU : 4.86 / 5.26 s | Elapsed : 4.00 / 5.00 s
 
--> 

Total memory usage is 102080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)