Verilog and VHDL状态机设计
Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : De...
Synchronous技术资料
📦 资源总数：73
💻 源代码：1815
📚 Synchronous全部资料 (73个)
Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces
Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces...
This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs t
This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs t...
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availabilit
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availabilit...
vhdl编写
vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inpu...
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, gen
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, gen...
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was rea
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was rea...
-- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right
-- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right...
CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b
CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b...
In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for un
In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for un...