源码文件
State Machine - |fpga2pc|STATE Name STATE.IDLE STATE.WRITE_2 STATE.WRITE_1 STATE.IDLE 0 0 0 STATE.WRITE_2 1 1 0 STATE.WRITE…
State+Machine 源代码
汇集 State+Machine 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
State Machine - |pc2fpga|STATE Name STATE.IDLE STATE.READ_2 STATE.READ_1 STATE.IDLE 0 0 0 STATE.READ_2 1 1 0 STATE.READ_1 1…
源码文件
State Machine - |pc2fpga|STATE Name STATE.IDLE STATE.READ_2 STATE.READ_1 STATE.IDLE 0 0 0 STATE.READ_2 1 1 0 STATE.READ_1 1…
源码文件
State Machine - |fpga2pc|STATE Name STATE.IDLE STATE.WRITE_2 STATE.WRITE_1 STATE.IDLE 0 0 0 STATE.WRITE_2 1 1 0 STATE.WRITE…
源码文件
State Machine - |lcd|state:inst2|next_state Name next_state.s9 next_state.s8 next_state.s7 next_state.s6 next_state.s5 next_state…
源码文件
State Machine - |ps2_mouse9|m2_nexts Name m2_nexts.m2_st46 m2_nexts.m2_st45 m2_nexts.m2_st44 m2_nexts.m2_st43 m2_nexts.m2_st42 m2…
源码文件
State Machine - |memory|state Name state.Idle state.sCS state.sdRD state.Idle 0 0 0 state.sdRD 1 0 1 state.sCS 1 1 0
源码文件
This directory contains the examples in the appendix of the "HDL compiler for Verilog" and "VHDL Compiler Reference Manual" These …
源码文件
State Machine - |median|cur_state Name cur_state.s15 cur_state.s14 cur_state.s13 cur_state.s12 cur_state.s11 cur_state.s10 cur_st…
源码文件
State Machine - |top|xulieji:inst7|seqdet:seqdet0|state Name state.D state.E state.A state.B state.C state.F state.G state.IDLE …