readme

design compile synthesis user guide

This directory contains the examples in the appendix of the
"HDL compiler for Verilog" and "VHDL Compiler Reference Manual"
These examples can be used to check the operation of the 
Design compiler or to see how HDL descriptions are synthesized
into gates. 

All the Verilog examples are in the sub-directory named "verilog".
The VHDL examples are contained in the "vhdl" sub-directory. Each 
example is contained in a seperate directory. 

The VHDL examples included are:

	Directory Name	Example
	-------------	--------------------------------
	moore		moore style Finite State Machine
	mealy		mealy style Finite State Machine
	ROM		ROM
	wave-gen	ROM implemented wave form generator
	smart-gen	Expanded version of the above
	add-sub		Expandable adder-subtractor 
	cnt-combin	Zero counter with combinational logic
	cnt-st		State machine version of Zero counter
	drink-st	State machine of Vending Machine
	drink-cnt	Count the coins method of Vending machine
	cla		32 bit Carry look ahead adder
	s2p-count	Serial to Parallel converter counts bits
	s2p-seq		Serial to Parallel converter Shifts bits
	pla		Programmable Logic array



The verilog examples included are:

	Directory Name	Example
	-------------	--------------------------------
	cla		16 bit Carry look ahead adder
	cnt-combin	Zero counter with combinational logic
	cnt-st		State machine version of Zero counter	
	drink-st	State machine implement of Vending Machine
	drink-cnt	Coin counting method of Vending Machine

Each directory contains the source code and a sample script to 
compile the design.  The design files have the same name as the
directory with a ".scr" appended for the script file, and ".vhd" 
appended for VHDL source code, and ".v" appended for verilog
source code. Several of the designs include a VHDL package. This 
is also included in the directory. 

The script file contains a description of the design and the 
design constraints associated with the design. The script can 
be printed out or executed from within the dc_shell.  For 
example, to run the example of the mealy machine in VHDL execute 
the following:

	% cd vhdl/mealy
	% dc_shell

	dc_shell> include mealy.scr

This will read in the design, set the constraints, and compile. 
Reports or schematics can then be generated.

Each script uses the 'class' library that is shipped with the 
software. A vendor specific library may be substituted by 
changing the appropriate entries in the script.

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
THESE EXAMPLES ARE FOR DEMONSTRATION ONLY. NOT ALL OF THEM WERE
FULLY SIMULATED. USE AT YOUR OWN RISK.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!