Slave+FIFO全部资料 - 虫虫开发者社区

2016-05-22 181 Slave+FIFO

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it...

2014-06-26 132 Slave+FIFO

2016-12-23 164 Slave+FIFO

2013-12-20 58 Slave+FIFO

In the absence of RAM, XC3000 FIFOs must be constructedwith registers. Using both flip-flops, on

2023-11-25 1 Slave+FIFO

本文通过介绍嵌入式处理器串口通信的特点，针对RAM 空间有限的小系统，提出了一种具有软件模拟FIFO 缓冲区的串行口通信模块，并详细说明了模块设计的方法。关键字串口通信模拟FIFO

2024-03-02 2 Slave+FIFO

In the absence of RAM, XC3000 FIFOs must be constructedwith registers. Using both flip-flops, on

2024-03-13 3 Slave+FIFO

异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统...

2013-08-08 185 Slave+FIFO

2015-10-26 135 Slave+FIFO

verilog实现I2C通信的slave模块源码状态机设位计可做I2C接口的仿真模型//`timescale 1ns/1psmodule I2C_slv (input [6:0] slv_id,input    &nbs...

2022-02-03 14 Slave+FIFO

Slave+FIFO