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Separate

  • The software and hardware development fields evolved along Separate paths through the end of the 20t

    The software and hardware development fields evolved along Separate paths through the end of the 20th century. We seem to have come full circle, however. The previously rigid hardware on which our programs run is softening in many ways. Embedded systems are largely responsible for this softening. These hidden computing systems drive the electronic products around us, including consumer products like digital cameras and personal digital assistants, office automation equipment like copy machines and printers, medical devices like heart monitors and ventilators, and automotive electronics like cruise controls and antilock brakes. Embedded systems force designers to work under incredibly tight time-tomarket, power consumption, size, performance, flexibility, and cost constraints. Many technologies introduced over the past two decades have sought to help satisfy these constraints. To understand these technologies, it is important to first distinguish the underlying embedded systems elements.

    标签: development the software hardware

    上传时间: 2017-08-15

    上传用户:cjf0304

  • 行为模式和同步事件调度操作

    The Reactor design pattern handles service requests that are delivered concurrently to an application by one or more clients. Each service in an application may consist of serveral methods and is represented by a Separate event handler that is responsible for dispatching service-specific requests.

    标签: 模式 操作 调度

    上传时间: 2013-10-15

    上传用户:libinxny

  • 低噪声,低压差稳压器的性能验证

      In an increasing trend, telecommunications, networking,audio and instrumentation require low noise power supplies.In particular, there is interest in low noise, lowdropout linear regulators (LDO). These components powernoise-sensitive circuitry, circuitry that contains noisesensitiveelements or both. Additionally, to conserve power,particularly in battery driven apparatus such as cellulartelephones, the regulators must operate with low input-tooutputvoltages.1 Devices presently becoming availablemeet these requirements (see Separate section, “A Familyof 20mVRMS Noise, Low Dropout Regulators”).

    标签: 低噪声 低压差稳压器 性能

    上传时间: 2013-10-30

    上传用户:yeling1919

  • 基于AVR单片机的闭环控制系统

      针对科研实验中对拉压千斤顶加载过程控制的需要,采用ATmega128单片机控制步进电机进而实现对执行系统的电动泵站实行自动控制。对力和位移的数据采集与处理及用步进电机控制电动泵站手柄的技术细节作了重点描述。通过单片机的A/D变换器对AMP放大模块采集的电桥信号作量化处理,千斤顶的操控手柄位置依电动油泵阀门开启的方向和大小作若干定位,单片机根据力或位移传感器信号,实时控制步进电机驱动手柄旋转到相应操控位置。   Abstract:   This article describes the use of ATmega128 AVR microcontroller series of DBS electric pumping stations and QF100/200 Separate twoway hydraulic jack to automate the process of manipulating the work of the technical content. Articles on force and displacement data acquisition and processing, and stepper motor control electric pump with the handle of the key technical details were described. Through the MCU’s A / D converter module is collected on the AMP amplification quantify the signal bridge, jack handle position control valve opening according to the direction of electric pumps for a number of positioning and size of the microcontroller based on force or displacement sensor signals, real-time control stepper motor drive control handle rotate to the appropriate location.  

    标签: AVR 单片机 闭环控制

    上传时间: 2014-01-16

    上传用户:hasan2015

  • PCA9541 2 to 1 I2C-bus master

    The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on Separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.

    标签: master C-bus 9541 PCA

    上传时间: 2013-10-09

    上传用户:3294322651

  • Using the P82B96 for bus inter

    The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signals permits interfacing ofthe P82B96 with other bus systems which Separate the forwardoutput path, from the backward input signal path.

    标签: P82B96 Using inter the

    上传时间: 2013-10-11

    上传用户:洛木卓

  • 87C576微控制器的在线编程

    The 87C576 includes two Separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.

    标签: 87C576 微控制器 编程

    上传时间: 2013-10-21

    上传用户:xiaozhiqban

  • UHF读写器设计中的FM0解码技术

       针对UHF读写器设计中,在符合EPC Gen2标准的情况下,对标签返回的高速数据进行正确解码以达到正确读取标签的要求,提出了一种新的在ARM平台下采用边沿捕获统计定时器数判断数据的方法,并对FM0编码进行解码。与传统的使用定时器定时采样高低电平的FM0解码方法相比,该解码方法可以减少定时器定时误差累积的影响;可以将捕获定时器数中断与数据判断解码相对分隔开,使得中断对解码影响很小,实现捕获与解码的同步。通过实验表明,这种方法提高了解码的效率,在160 Kb/s的接收速度下,读取一张标签的时间约为30次/s。 Abstract:  Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator, the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level, the method could reduce the accumulation of timing error and could relatively Separate capture timer interrupt and the data judgment for decoding, so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding, at 160 Kb/s receiving speed, the time of the interrogator to read a tag is about 30 times/s.

    标签: UHF FM0 读写器 解码技术

    上传时间: 2013-11-10

    上传用户:liufei

  • LPC1850 Cortex-M3内核微控制器数据手册

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withSeparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.

    标签: Cortex-M 1850 LPC 内核微控制器

    上传时间: 2014-12-31

    上传用户:zhuoying119

  • LPC4300系列ARM双核微控制器产品数据手册

    The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withSeparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals

    标签: 4300 LPC ARM 双核微控制器

    上传时间: 2013-10-28

    上传用户:15501536189