基于scilab软件的gmsk信号的调制
上传时间： 2013-12-04
上传用户：lanhuaying
使用Scilab编写的粒子群算法，例子比较简单，无混沌搜索
上传时间： 2017-06-15
上传用户：lnnn30
基于Scilab的粒子群算法代码，Scilab是一个功能和matlab差不多的开源软件
上传时间： 2017-09-14
上传用户：小宝爱考拉
科学计算自由软件SCILAB基础教程，使用讲解
上传时间： 2021-10-10
上传用户：lanxin_eeworm
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
小波分解源代码，基于Scilab！Scilab是一个OpenSource的类似matlab的工具，通过该源代码可以为开发小波分析提供参考！
上传时间： 2015-09-25
上传用户：王小奇
RTOS-嵌入式系统微内核概念和实现 Realtime Operating Systems Concepts and Implementation of Microkernels for Embedded Systems Dr. Jürgen Sauermann, Melanie Thelen
标签： Implementation Microkernels Operating Concepts
上传时间： 2014-01-03
上传用户：zgu489
BP人工神经网络算法，用java代码实现，用scilab图像显示，案例是港口吞吐量的预测
上传时间： 2016-10-28
上传用户：思琦琦
Graphic Library for screen pg12864 handled by lpc21xx controller. Project was developed with IAR embedded workbench.
标签： controller developed Graphic Library
上传时间： 2017-04-23
上传用户：duoshen1989
