搜索：SDC
找到约 19 项符合「SDC」的查询结果
结果 19
按分类筛选
https://www.eeworm.com/dl/655/463037.html
微处理器开发
this is an open source software for FAT file system over MMC SDC
this is an open source software for FAT file system over MMC SDC
https://www.eeworm.com/dl/894292.html
技术资料
该程序包是SD卡_MMC卡控制器SDC的verilog语言包
该程序包是SD卡_MMC卡控制器SDC的verilog语言包
https://www.eeworm.com/dl/fpga/doc/32212.html
教程资料
传统时序分析器TAN到基于SDC的Timequest时序分析器转换
03_传统时序分析器TAN到基于SDC的Timequest时序分析器转换
https://www.eeworm.com/dl/kbcluoji/39042.html
可编程逻辑
传统时序分析器TAN到基于SDC的Timequest时序分析器转换
03_传统时序分析器TAN到基于SDC的Timequest时序分析器转换
https://www.eeworm.com/dl/534/159514.html
其他
数字音频广播中三个子信道之一的SDC信道的解码和在pc机上的功能实现
数字音频广播中三个子信道之一的SDC信道的解码和在pc机上的功能实现
https://www.eeworm.com/dl/517756.html
笔记
Vivado时序约束
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. SDC has been in use and evolving for more than 20 years, making it the ...
https://www.eeworm.com/dl/971055.html
技术资料
Multicycle setting
Multicycle setting of SDC in synthesis tools
https://www.eeworm.com/dl/831600.html
技术资料
vivado集成开发环境时序约束介绍
本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Desi ...