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S-V MATLAB

  • MATLAB揭秘

    MATLAB揭秘,详细地介绍了matlab

    标签: MATLAB

    上传时间: 2013-10-11

    上传用户:blans

  • Matlab数学手册

    Matlab数学手册,非常实用

    标签: Matlab 数学手册

    上传时间: 2013-10-31

    上传用户:raron1989

  • MATLAB入门

    matlab

    标签: MATLAB

    上传时间: 2013-12-25

    上传用户:jackgao

  • matlab作图代码

    matlab作图代码

    标签: matlab 代码

    上传时间: 2013-11-03

    上传用户:xiaojie

  • MATLAB实验指导书(信号与系统)

    MATLAB实验指导书(信号与系统)

    标签: MATLAB 实验指导书 信号与系统

    上传时间: 2014-01-15

    上传用户:toyoad

  • matlab工具箱函数汇总

    matlab工具箱函数汇总

    标签: matlab 工具箱 函数

    上传时间: 2013-10-23

    上传用户:风之骄子

  • matlab图形句柄介绍

    Matlab图形句柄介绍,方便查找

    标签: matlab 图形

    上传时间: 2013-11-18

    上传用户:wdq1111

  • MATLAB编程

    MATLAB编程

    标签: MATLAB 编程

    上传时间: 2013-12-15

    上传用户:hoperingcong

  • [Matlab.PDF电子教程].Matlab5.2manual

    [Matlab.PDF电子教程].Matlab5.2manual

    标签: Matlab manual 5.2

    上传时间: 2013-11-01

    上传用户:xz85592677

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman