Pipelined
共 14 篇文章
Pipelined 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 14 篇文章，持续更新中。
Systematic Design for Optimisation of Pipelined ADCs.pdf
资料->【E】光盘论文->【E5】英文书籍->Systematic Design for Optimisation of Pipelined ADCs.pdf
一种基于FPGA的FFT分析方法
<p> DFT(Discrete Fourier Transformation)是数字信号分析与处理如图形、语音及图像等领域的重要变换工具，直接计算DFT的计算量与变换区间长度N的平方成正比。当N较大时，因计算量太大，直接用DFT算法进行谱分析和信号的实时处理是不切实际的。快速傅立叶变换(Fast Fourier Transformation，简称FFT)使DFT运算效率提高1～2个数量
ADC的分类比较及性能指标
<p>1A/D转换器的分类与比较</p><p>AD转换器（ADC）是模拟系统与数字系统接口的关键部件，长期以米一直被广泛应用于雷达、通信、电子对抗、声纳、卫星、导弹、测控系统、地震、医疗、仪器仪表、图像和音频等领域。随者计算机和通信产业的迅猛发展，进一步推动了ADC在便携式设备上的应用并使其有了长足进步，ADC正逐步向高速、高精度和低功耗的方向发展。</p><p>通常，AD转换器具有三个基本功能：
On a distributed algorithm based on FPGA pipelined FIR filter of the article.
On a distributed algorithm based on FPGA pipelined FIR filter of the article.
A programmable digital signal processor (PDSP) is a special-purpose microprocessor with specialized
A programmable digital signal processor (PDSP) is a special-purpose microprocessor
with specialized architecture and instruction set for implementing DSP
algorithms. Typical architectural features i
The Hilbert Transform is an important component in communication systems, e.g. for single sideband m
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operat
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in li
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys.
The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemen
DFT(Discrete Fourier Transformation)是数字信号分析与处理如图形、语音及图像等领域的重要变换工具
DFT(Discrete Fourier Transformation)是数字信号分析与处理如图形、语音及图像等领域的重要变换工具，直接计算DFT的计算量与变换区间长度N的平方成正比。当N较大时，因计算量太大，直接用DFT算法进行谱分析和信号的实时处理是不切实际的。快速傅立叶变换(Fast Fourier Transformation，简称FFT)使DFT运算效率提高1～2个数量级。其原因是当N较
Computer Architecture pipelined implementation simulator
Computer Architecture pipelined
implementation simulator
带有增益提高技术的高速CMOS运算放大器设计
<span style="color: rgb(0, 0, 0); font-family: 'Trebuchet MS', Arial; line-height: 21px; ">设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构，利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度，100 MS/s采样频率的高速流
Self timed pipelined adder
Self timed pipelined adder
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier
In communication systems channel poses an important role. channels can convolve many different kind
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
一种增益增强型套筒式运算放大器的设计
设计了一种用于高速ADC中的全差分套筒式运算放大器.从ADC的应用指标出发,确定了设计目标,利用开关电容共模反馈、增益增强等技术实现了一个可用于12 bit精度、100 MHz采样频率的高速流水线(Pipelined)ADC中的运算放大器.基于SMIC 0.13 μm,3.3 V工艺,Spectre仿真结果表明,该运放可以达到105.8 dB的增益,单位增益带宽达到983.6 MHz,而功耗仅为2