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VHDL中Loop动态条件的可综合转化.pdf
资料->【C】嵌入系统->【C2】IC设计与FPGA->【3】其它->【Verilog HDL、VHDL、硬件描述语言】->VHDL中Loop动态条件的可综合转化.pdf...
Phase Locked Loop
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* Module Description: * This main control loop shell provides everything required for a basic uIP
* Module Description: * This main control loop shell provides everything required for a basic uIP ...
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This file contains a loop-back test for the audio part of the SmartRF04EB
This file contains a loop-back test for the audio part of the SmartRF04EB...
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three-phase Permanent Magnet Synchronous Motor(PMSM) velocity control DSP program
three-phase Permanent Magnet Synchronous Motor(PMSM) velocity control DSP program...
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Analysis of blind data hiding using discrete cosine transform phase modulation。
Analysis of blind data hiding using discrete cosine transform phase modulation。...
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Results of the Adaptive Multi-Rate (AMR) noise suppression selection phase
Results of the Adaptive Multi-Rate (AMR) noise suppression selection phase...
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this is file used for design of three phase current controller
this is file used for design of three phase current controller...
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A Top-Down Verilog-A Design on the digital phase-lockedmloop
A Top-Down Verilog-A Design on the digital phase-lockedmloop...
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calculate and plot M-PSK for AWGN channel with exact phase
calculate and plot M-PSK for AWGN channel with exact phase...
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Sample ADA program...How to create hello world....programs on IF loop and switch case
Sample ADA program...How to create hello world....programs on IF loop and switch case...