The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
上传时间： 2013-11-15
上传用户：fklinran
深入浅出AVR单片机思路清晰，以AVR单片机为载体，介绍了初学单片机所必须掌握的专业知识。书中语言严谨但不乏幽默风趣，配以大量的照片、图示和实例程序，使读者在愉悦中完成专业知识的学习，并培养了学习嵌入式系统的兴趣。本书在讲述AVR单片机的同时，更注重于对读者学习和设计能力的启发、培养，帮助他们养成“从实践中来，到实践中去”的科学方法论，为进一步的学习创造了基础。 本书讲述浅显、内容丰富、编排合理、实例详尽。首先介绍了如何阅读器件资料的方法，然后熟悉ICCAVR集成开发环境并搭建实验开发装置，接着从实际应用出发，启发式地介绍AVR单片机的常用资源和对应软件方法，最后较为全面地补充了从事嵌入式系统开发要扩展的软件知识。 第1篇 Are you ready？ 第1章 学会阅读Datasheet 1.1 如何阅读PDF文件，如何获得Datasheet文件 1.2 Datasheet告诉我们些什么 1.3 如何看懂AVR的Datasheet 1.4 如何得到帮助 1.5 汇编语言执行时间的计算方法 1.6 ATmega48/88/168常用熔丝的作用及其配置方法 1.7 对误烧写为外部时钟模式的解锁方法 实例1 阅读74HC595 Datasheet 第2章 深入开发环境 2.1 认识ICC编译环境 2.2 事半功倍的代码生成器 2.3 ICC之不得不说的故事 2.4 AVR最小系统和下载线DIY 实例2 AVR最小系统DIY第2篇 Let\'s go！ 第3章 从跑马灯开始 3.1 输入/输出界面 3.1.1 单片机的输入/输出设备——引脚 3.1.2 “芯”里有数——数码管显示 3.1.3 单片机的输入/输出设备——从按键到键盘 3.2 用ATmega48/88/168单片机端口驱动数码管 3.3 操纵ATmega48/88/168单片机端口 3.4 端口内建上拉电阻的使用 3.5 端口位操作 实例3 跑马灯 实例4 数码管的显示（上） 实例5 数码管的显示（下） 实例6 矩阵键盘 第4章 对不起接个电话 4.1 十万火急——中断 4.2 中断的特性 4.3 使用中断时的注意事项 4.4 ATmega48/88/168单片机有哪些中断源 4.5 如何编写一个中断的服务程序代码 4.6 ATmega48/88/168单片机中断的开关控制 4.7 ATmega48/88/168中断标志位 4.8 ATmega48/88/168中断优先级 4.9 ATmega48/88/168单片机中断向量 4.10 中断与查询之争 4.11 用查询方式响应外设中断 4.12 中断误触发 4.13 前后台与原子操作 实例7 中断唤醒的键盘扫描 实例8 旋转编码器 第5章 一秒究竟有多长 5.1 单片机与时间 5.2 软件延时 5.3 不需要加载的“自由计时器” 5.4 通过重加载控制定时中断周期 5.5 使用代码生成器生成定时器1初始化代码 5.6 定时器的其他工作模式 5.7 PWM波及其应用简介 5.8 人类能看懂的电子时钟——实时时钟简介 实例9 闪烁的灯 实例10 渐明渐暗的灯 实例11 复杂闪烁控制 第6章 电量低 6.1 从猜数游戏到A/D转换器 6.2 ATmega48/88/168的A/D转换器 6.3 ATmega48/88/168单片机中与A/D相关的引脚 6.4 ATmega48/88/168单片机中与A/D相关的寄存器 6.5 使用A/D时需要注意些什么 6.6 怎样知道A/D转换完成 6.7 读取A/D的转换结果 6.8 使用代码生成器生成ADC初始化代码 6.9 书写具有工程结构的初始化代码 6.10 电量计原理概述 …… 第7章 正在过收费站 第8章 包装的学问 第9章 傻孩子求职记 第10章 MISSION UPDATE第3篇 Code Name C 第11章 朝花夕拾 第12章 指针都是纸老虎 第13章 来自身边的启示 第14章 初识嵌入式系统
上传时间： 2014-05-05
上传用户：佳期如梦
CAN与RS232转换节点的设计与实现 介绍将CAN总线接口与RS232总线接口相互转换的设计方法和2种总线电平转换关系，实现CAN总线与各模块的接口设计，制定了相应的软硬件设计方案，并给出软件设计流程图以及部分硬件设计原理图。为CAN总线与RS232总线互联提供了一种方法，对CAN总线与RS232总线接口设备的互联和广泛应用的实现具有重要意义。关键词：CAN总线；RS-232总线；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
上传时间： 2013-11-04
上传用户：leesuper
CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy
上传时间： 2014-12-28
上传用户：gououo
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
上传时间： 2013-11-05
上传用户：透明的心情
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上传时间： 2013-11-14
上传用户：JIMMYCB001
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-11-13
上传用户：我累个乖乖
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上传时间： 2013-11-01
上传用户：KSLYZ
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-11
上传用户：gundamwzc
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
上传时间： 2013-11-16
上传用户：qingdou
