·文件列表: 用于MPEG4解码的源代码 .....................\BUILD .....................\.....\CVS .....................\.....\WIN32 .....................\.....\.....\console.dsp
上传时间： 2013-08-01
上传用户：xg262122
·Windows下面的MP4解码源代码文件列表: mpeg4decsrc ...........\DECORE ...........\......\BUILD ...........\......\.....\CVS ...........\......\.....\WIN32 ...........\......
上传时间： 2013-05-27
上传用户：a673761058
·MPEG4编码库源代码(VC)文件列表(点击判断是否您需要的文件): mpeg4encsrc ...........\encore ...........\......\Acknowledgement.txt ...........\......\build ...........\......\.....\CVS
上传时间： 2013-04-24
上传用户：q123321
·MPEG4的编码文件列表： mpeg4encsrc ...........\encore ...........\......\Acknowledgement.txt ...........\......\build ...........\......\.....\CVS ...........\......\..
上传时间： 2013-06-25
上传用户：水口鸿胜电器
viterbi译码器的一种fpga实现.是一个cs252\r\n的project的result\r\n供大家研究用
上传时间： 2013-09-06
上传用户：dsgkjgkjg
How we make connection with Proteus and the LCD, (project included)
标签： connection Proteus make with
上传时间： 2013-09-24
上传用户：lihairui42
工作环境设置及软件安装这章介绍工作环境的设置及软件安装方面知识。为什么要进行工作环境设置呢？因为现在的PCB 工程师要设计的文件很多。文件多了如果不进行管理就会很混乱，导致以后的维护十分困难。所以要从刚开始学习的时候养成一个好的操作习惯，这是很有必要的。2.1 建立自己的工作目录在电脑的桌面上打开我的电脑，在我的电脑中打开D盘。在D 盘中建立三个文件夹。分别为“D：\EDA”“D：\EDA_LIB”“D：\EDA_PROJECT 三个文件夹”。如下图所示：图2-1-1 “建立工作目录”建立好三个文件夹后，在这三个文件夹中分别另建立一个新文夹，并命名为Protel99se。三个文件夹的作用分别是：EDA文件夹是用来存放安装文件；EDA—LIB 文件夹是用来存放元件库。EDA—PROJECT 文件夹是用来存放设计数据。2.2 对Protel 99se 进行安装设置好工作目录后，就可以对软件进行安装。图2-1-2就是Protel 99se的安装程序。其中“Protel99SP6”是升级补丁，“Protel99 汉化”是汉化文件。（1）双击Setup 安装图标对软件进行安装。
上传时间： 2013-11-16
上传用户：swz13842860183
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
Abstract: Build a composite amplifier featuring high gain, wide bandwidth, good DC accuracy and low distortion
上传时间： 2014-12-23
上传用户：JasonC
上传一分自己用得顺心的AD10集成库
上传时间： 2013-11-15
上传用户：eastgan
