PLL设计
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资源总数
500
PLL设计 全部资料 500 份
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz
2016-10-08
123
MAX7044是基于晶振PLL 的VHF/UHF发射器芯片
MAX7044是基于晶振PLL 的VHF/UHF发射器芯片，在300 MHz～450 MHz频率范围内发射OOK/ASK数据，数据速率达到100 kbps，输出功率+13 dBm(50Ω负载)，电源电压+2.1～+3.6 V，电流消耗在2....
2017-05-06
133
单片机控制的DDS+PLL宽带频率合成器
介绍了DDS芯片AD9852和锁相环芯片ADF4113的主要工作原理和功能特点.介绍了DDS+PLL混合频率合成技术的原理和应用.给出了用单片机控制DDS+PLL实现2～4GHz宽带跳频频率合成器的设计电路,并给出实验结果.
2024-12-03
7
％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated
％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,t...
2015-09-28
121
CMOS PLL Synthesizers：analysis and design -- a very good book by Keliu Shu Edgar Sánchez-Sinencio a
CMOS PLL Synthesizers：analysis and design -- a very good book by Keliu Shu Edgar Sánchez-Sinencio and published by Spri...
2013-12-24
106
Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range
Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any...
2014-11-25
117