altera i2c slave ip核verilog 编写
altera i2c slave ip核verilog 编写...
altera i2c slave ip核verilog 编写...
This an exercise in using finite state machines.基于ALTERA的DE2开发 平台,设计一个有限状态机FSM(finite state machines)....
Simulation with Modelsim Simulation with Modelsim.rar...
modelsim + debussy脚本...
modelsim+dc开发的4级流水线结构的MIPS CPU,完成基本的逻辑运算和跳转。测试程序为希尔排序,结果正确。...