Microsoft Hyper-V 源代码

module latch_1(q,d,clk); output q; input d,clk; assign q = clk ? d : q; endmodule

module gate2(F,A,B,C,D); input A,B,C,D; output F; assign F=(A&B)|(B&C&D); endmodule

module code_83(din, dout); input[7:0] din; output[2:0] dout; function[2:0] code; input[7:0] din; if (din[7]) code = 3'd7…

module gate3(F,A,B,C,D); input A,B,C,D; output F; reg F; always @(A or B or C or D) begin F=(A&B)|(B&C&D); end endmodule

module encoder8_3(none_on,outcode,a,b,c,d,e,f,g,h); output none_on; output[2:0] outcode; input a,b,c,d,e,f,g,h; reg[3:0] outte…

module tri_1(in,en,out); input in,en; output out; tri out; bufif1 b1(out,in,en); endmodule

module gate1(F,A,B,C,D); input A,B,C,D; output F; nand(F1,A,B); and(F2,B,C,D); or(F,F1,F2); endmodule

module decode47(a,b,c,d,e,f,g,D3,D2,D1,D0); output a,b,c,d,e,f,g; input D3,D2,D1,D0; reg a,b,c,d,e,f,g; always @(D3 or D2 or…

module bidir2(bidir,en,clk); inout[7:0] bidir; input en,clk; reg[7:0] temp; assign bidir= en ? temp : 8'bz; always @(posedge …

module ram256x8(data,address,we,inclock,outclock,q); input[7:0] data; input[7:0] address; input we,inclock,outclock; output[7:…