Microsoft Hyper-V 源代码

module div_4(clk50m,clk1_8m); input clk50m; output clk1_8m; reg [12:0] acc ; // 13 bits total! always @(posedge …

// megafunction wizard: %LPM_RAM_DP% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ===================…

// megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ===========================…

// megafunction wizard: %LPM_FIFO+% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ========================…

//`include "F:\jeffie\quartus\lcdfinal\lcdfinal.v" //`include "F:\jeffie\quartus\lcdfinal\LCD_TEST.v" //`include "F:\jeffie\quar…

module decoder_38(out,in); output[7:0] out; input[2:0] in; reg[7:0] out; always @(in) begin case(in) 3'd0: out=8'b111111…

module DFF2(q,qn,d,clk,set,reset); input d,clk,set,reset; output q,qn; reg q,qn; always @(posedge clk) begin if (reset) …

module DFF1(q,qn,d,clk,set,reset); input d,clk,set,reset; output q,qn; reg q,qn; always @(posedge clk or negedge set or nege…

module latch_2(q,d,clk,set,reset); output q; input d,clk,set,reset; assign q = reset ? 0 : (set ? 1 : (clk ? d : q)); endmodul…

module tri_2(out,in,en); output out; input in,en; assign out = en ? in : 'bz; endmodule