LPC master verilog source(内附LPC标准协议文档)
用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计 ...
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用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计 ...
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-...
-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on s...
Accessing Atmel AT45Dxxx dataflash on STK500 .Sets up the HW SPI in Master mode...
Slave mode FX2LP Firmware for raw-data transfer from an external master (altera FPGA)...
code for i2c communication between master and slave in a system using AVR MCU...
This directory contains the miniport driver for INI-9100U/UW PCI_UltraSCSI Bus Master Controllers. T...
spi 通信的master部分使用的verilog语言实现,可以做为你的设计参考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,...
SPI communication between a single master and slave. Including a LCD controller that display the rec...