The Controller Area Network (CAN) is a serial, asynchronous, multi-master communication protocol forconnecting electronic control modules, sensors and actuators in automotive and industrial applications.With the SJA1000, Philips Semiconductors provides a stand-alone CAN controller which is more than a simpleeplacement of the PCA82C200.Attractive features are implemented for a wide range of applications, supporting system optimization, diagnosisand maintenance.
标签： Stand-alone contro 1000 SJA
上传时间： 2013-11-18
上传用户：yxgi5
MSP430系列单片机C语言程序设计与开发MSP430系列是一个具有明显技术特色的单片机品种。关于它的硬件特性及汇编语言程序设计已在《MSP430系列超低功耗16位单片机的原理与应用》及《MSP430系列 FLASH型超低功耗16位单片机》等书中作了全面介绍。《MSP430系列单片机C语言程序设计与开发》介绍IAR公司为MSP430系列单片机配备的C程序设计语言C430。书中叙述了C语言的基本概念、C430的扩展特性及C库函数；对C430的集成开发环境的使用及出错信息作了详尽的说明；并以MSP430F149为例，对各种应用问题及外围模块操作提供了典型的C程序例程，供读者在今后的C430程序设计中参考。 《MSP430系列单片机C语言程序设计与开发》可以作为高等院校计算机、自动化及电子技术类专业的教学参考书，也可作为工程技术人员设计开发时的技术资料。MSP430系列超低功耗16位单片机的原理与应用目录MSP430系列单片机C语言程序设计与开发 目录 第1章 C语言基本知识1.1 标识符与关键字11.1.1 标识符11.1.2 关键字11.2 数据基本类型21.2.1 整型数据21.2.2 实型数据31.2.3 字符型数据41.2.4 各种数据转换关系61.3 C语言的运算符71.3.1 算术运算符71.3.2 关系运算符和逻辑运算符71.3.3 赋值运算符81.3.4 逗号运算符81.3.5 ? 与 ：运算符81.3.6 强制转换运算符91.3.7 各种运算符优先级列表91.4 程序设计的三种基本结构101.4.1 语句的概念101.4.2 顺序结构111.4.3 选择结构121.4.4 循环结构141.5 函数181.5.1 函数定义181.5.2 局部变量与全局变量191.5.3 形式参数与实际参数201.5.4 函数调用方式201.5.5 函数嵌套调用211.5.6 变量的存储类别221.5.7 内部函数和外部函数231.6 数组231.6.1 一维数组241.6.2 多维数组241.6.3 字符数组261.7 指针271.7.1 指针与地址的概念271.7.2 指针变量的定义281.7.3 指针变量的引用281.7.4 数组的指针281.7.5 函数的指针301.7.6 指针数组311.8 结构和联合321.8.1 结构定义321.8.2 结构类型变量的定义331.8.3 结构类型变量的初始化341.8.4 结构类型变量的引用341.8.5 联合341.9 枚举361.9.1 枚举的定义361.9.2 枚举元素的值371.9. 3 枚举变量的使用371.10 类型定义381.10.1 类型定义的形式381.10.2 类型定义的使用381.11 位运算391.11.1 位运算符391.11.2 位域401.12 预处理功能411.12.1 简单宏定义和带参数宏定义411.12.2 文件包含431.12.3 条件编译命令44第2章 C430--MSP430系列的C语言2.1 MSP430系列的C语言452.1.1 C430概述452.1.2 C430程序设计工作流程462.1.3 开始462.1.4 C430程序生成472.2 C430的数据表达482.2.1 数据类型482.2.2 编码效率502.3 C430的配置512.3.1 引言512.3. 2 存储器分配522.3.3 堆栈体积522.3.4 输入输出522.3.5 寄存器的访问542.3.6 堆体积542.3.7 初始化54第3章 C430的开发调试环境3.1 引言563.1.1 Workbench特性563.1.2 Workbench的内嵌编辑器特性563.1.3 C编译器特性573.1. 4 汇编器特性573.1.5 连接器特性583.1.6 库管理器特性583.1.7 C?SPY调试器特性593.2 Workbench概述593.2.1 项目管理模式593.2.2 选项设置603.2.3 建立项目603.2.4 测试代码613.2.5 样本应用程序613.3 Workbench的操作623.3.1 开始633.3.2 编译项目683.3.3 连接项目693.3.4 调试项目713.3.5 使用Make命令733.4 Workbench的功能汇总753.4.1 Workbench的窗口753.4.2 Workbench的菜单功能813.5 Workbench的内嵌编辑器993.5.1 内嵌编辑器操作993.5.2 编辑键说明993.6 C?SPY概述1013.6.1 C?SPY的C语言级和汇编语言级调试1013.6.2 程序的执行1023.7 C?SPY的操作1033.7.1 程序生成1033.7.2 编译与连接1033.7.3 C?SPY运行1033.7.4 C语言级调试1043.7.5 汇编级调试1113.8 C?SPY的功能汇总1133.8.1 C?SPY的窗口1133.8.2 C?SPY的菜单命令功能1203.9 C?SPY的表达式与宏1323.9.1 汇编语言表达式1323.9.2 C语言表达式1333.9.3 C?SPY宏1353.9.4 C?SPY的设置宏1373.9.5 C?SPY的系统宏137 第4章 C430程序设计实例4.1 程序设计与调试环境1434.1.1 程序设计调试集成环境1434.1.2 设备连接1444.1.3 ProF149实验系统1444.2 数值计算1454.2.1 C语言表达式1454.2.2 利用MPY实现运算1464.3 循环结构1474.4 选择结构1484.5 SFR访问1494.6 RAM访问1504.7 FLASH访问1514.8 WDT操作1534.8. 1 WDT使程序自动复位1534.8.2 程序对WATCHDOG计数溢出的控制1544.8.3 WDT的定时器功能1554.9 Timer操作1554.9.1 用Timer产生时钟信号1554.9.2 用Timer检测脉冲宽度1564.10 UART操作1574.10.1 点对点通信1574.10.2 点对多点通信1604.11 SPI操作1634.12 比较器操作1654.13 ADC12操作1674.13.1 单通道单次转换1674.13.2 序列通道多次转换1684.14 时钟模块操作1704.15 中断服务程序1714.16 省电工作模式1754.17 调用汇编语言子程序1764.17.1 程序举例1764.17.2 生成C程序调用的汇编子程序177第5章 C430的扩展特性5.1 C430的语言扩展概述1785.1.1 扩展关键字1785.1.2 #pragma编译命令1785.1.3 预定义符号1795.1.4 本征函数1795.1.5 其他扩展特性1795.2 C430的关键字扩展1795.2.1 interrupt1805.2.2 monitor1805.2.3 no_init1815.2.4 sfrb1815.2.5 sfrw1825.3 C430的 #pragma编译命令1825.3.1 bitfields=default1825.3.2 bitfields=reversed1825.3.3 codeseg1835.3.4 function=default1835.3.5 function=interrupt1845.3.6 function=monitor1845.3.7 language=default1845.3.8 language=extended1845.3.9 memory=constseg1855.3.10 memory=dataseg1855.3.11 memory=default1855.3.12 memory=no_init1865.3.13 warnings=default1865.3.14 warnings=off1865.3.15 warnings=on1865.4 C430的预定义符号1865.4.1 DATE1875.4.2 FILE1875.4.3 IAR_SYSTEMS_ICC1875.4.4 LINE1875.4.5 STDC1875.4.6 TID1875.4.7 TIME1885.4.8 VER1885.5 C430的本征函数1885.5.1 _args＄1885.5.2 _argt＄1895.5.3 _BIC_SR1895.5.4 _BIS_SR1905.5.5 _DINT1905.5.6 _EINT1905.5.7 _NOP1905.5.8 _OPC1905.6 C430的汇编语言接口1915.6.1 创建汇编子程序框架1915.6.2 调用规则1915.6.3 C程序调用汇编子程序1935.7 C430的段定义1935.7.1 存储器分布与段定义1945.7.2 CCSTR段1945.7.3 CDATA0段1945.7.4 CODE段1955.7.5 CONST1955.7.6 CSTACK1955.7.7 CSTR1955.7.8 ECSTR1955.7.9 IDATA01965.7.10 INTVEC1965.7.11 NO_INIT1965.7.12 UDATA0196第6章 C430的库函数6.1 引言1976.1.1 库模块文件1976.1.2 头文件1976.1.3 库定义汇总1976.2C 库函数参考2046.2.1 C库函数的说明格式2046.2.2 C库函数说明204第7章 C430编译器的诊断消息7.1 编译诊断消息的类型2307.2 编译出错消息2317.3 编译警告消息243附录 AMSP430系列FLASH型芯片资料248附录 BProF149实验系统251附录 CMSP430x14x.H文件253附录 DIAR MSP430 C语言产品介绍275
上传时间： 2014-05-05
上传用户：253189838
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
上传时间： 2013-11-23
上传用户：weixiao99
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
基于单片机的汽车多功能报警系统设计The Design of Automobile Multi-function AlarmingBased on Single Chip Computer刘法治赵明富宁睡达(河 南 科 技 学 院 ，新 乡 453 00 3)摘要介绍了一种基于单片机控制的汽车多功能报警系统，它能对汽车的润滑系统油压、制动系统气压、冷却系统温度、轮胎欠压及防盗进行自动检测，并在发现异常情况时，发出声光报警。阐述了该报警系统的硬件组成及软件设计方法。关键词单片机传感器数模转换报警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly场thesystem. Audio and visual alarms wil be provided under abnormal conditions厂The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽车多功能报苦器硬件系统设计根据 系 统 实际需要和产品性价比，选用ATMEL公司新生产的采用CMOs工艺的低功耗、高性能8位单片机AT89S52作为系统的控制器。AT89S52的片内有8k Bytes LSP Flash闪烁存储器，可进行100(〕次写、擦除操作;256Bytes内部数据存储器(RAM);3 2 根可编程输N输出线;2个可编程全双工串行通道;看门狗(WTD)电路等。系统由传感器、单片机、模数转换器、无线信号发射电路、指示灯驱动电路、声光报警驱动电KD一9563，发出三声二闪光。并触发一个高电平，驱动无线信号发射电路。
上传时间： 2013-11-09
上传用户：gxmm
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
随着HDL Hardware Description Language 硬件描述语言语言综合工具及其它相关工具的推广使广大设计工程师从以往烦琐的画原理图连线等工作解脱开来能够将工作重心转移到功能实现上极大地提高了工作效率任何事务都是一分为二的有利就有弊我们发现现在越来越多的工程师不关心自己的电路实现形式以为我只要将功能描述正确其它事情交给工具就行了在这种思想影响下工程师在用HDL语言描述电路时脑袋里没有任何电路概念或者非常模糊也不清楚自己写的代码综合出来之后是什么样子映射到芯片中又会是什么样子有没有充分利用到FPGA的一些特殊资源遇到问题立刻想到的是换速度更快容量更大的FPGA器件导致物料成本上升更为要命的是由于不了解器件结构更不了解与器件结构紧密相关的设计技巧过分依赖综合等工具工具不行自己也就束手无策导致问题迟迟不能解决从而严重影响开发周期导致开发成本急剧上升 目前我们的设计规模越来越庞大动辄上百万门几百万门的电路屡见不鲜同时我们所采用的器件工艺越来越先进已经步入深亚微米时代而在对待深亚微米的器件上我们的设计方法将不可避免地发生变化要更多地关注以前很少关注的线延时我相信ASIC设计以后也会如此此时如果我们不在设计方法设计技巧上有所提高是无法面对这些庞大的基于深亚微米技术的电路设计而且现在的竞争越来越激励从节约公司成本角度出 也要求我们尽可能在比较小的器件里完成比较多的功能 本文从澄清一些错误认识开始从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧本文对读者的技能基本要求是熟悉数字电路基本知识如加法器计数器RAM等熟悉基本的同步电路设计方法熟悉HDL语言对FPGA的结构有所了解对FPGA设计流程比较了解
上传时间： 2013-11-06
上传用户：asdfasdfd
为提升虚拟仪器传输速率与实时性能，扩展监测范围，在VC的软件平台上设计了一种全功能虚拟示波器。与传统虚拟示波器相比，该系统采用嵌入式系统完成信号采集，采用工业以太网为传输介质，通过线性插值算法和多线程编程思想，实现波形显示、参数计算、频谱分析以及波形存储及回放功能。实验结果表明，该虚拟示波器可以实现20 kHz采样频率下的波形精确显示，达到预期的各项指标。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
上传时间： 2013-11-25
上传用户：wbwyl
同步技术是跳频通信系统的关键技术之一，尤其是在快速跳频通信系统中，常规跳频通信通过同步字头携带相关码的方法来实现同步，但对于快跳频来说，由于是一跳或者多跳传输一个调制符号，难以携带相关码。对此引入双跳频图案方法，提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息，克服了快速跳频难以携带相关码的困难。分析了同步性能，仿真结果表明该方案同步时间短、虚警概率低、捕获概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上传时间： 2013-11-23
上传用户：mpquest
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上传时间： 2014-01-17
上传用户：Altman
