The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
标签: appropriately The endpoints following
上传时间: 2013-12-02
上传用户:dianxin61
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHz.
标签: SDRAM controller simulated designed
上传时间: 2013-12-18
上传用户:yiwen213
All programs were tested using a breadboard containing a DS80C320, 32K Program memory, 32K Data memory, two 8-segment bar graph LEDs/drivers, and an 11.0592 MHz crystal. The four 8-segment bar graph LEDs/drivers were connected to ports 1, and 3 to display their pins states.
标签: breadboard containing 32K programs
上传时间: 2016-03-29
上传用户:qq1604324866
CC1100是一种低成本真正单片的UHF收发器,为低功耗无线应用而设计。电路主要设定为在315、433、868和915MHz的ISM(工业,科学和医学)和SRD(短距离设备)频率波段,也可以容易地设置为300-348 MHz、400-464 MHz和800-928 MHz的其他频率。 RF收发器集成了一个高度可配置的调制解调器。这个调制解调器支持不同的调制格式,其数据传输率可达500kbps。通过开启集成在调制解调器上的前向误差校正选项,能使性能得到提升。 CC1100为数据包处理、数据缓冲、突发数据传输、清晰信道评估、连接质量指示和电磁波激发提供广泛的硬件支持。
上传时间: 2014-10-09
上传用户:caixiaoxu26
A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced.The 1 Hz—l MHz input measured pulse signals of the digital ii‘equency meter can be used for measuring frequency,period,pulse width and duty ratio,etc.The test results stably display O71 3 seven—segment numeric tubes,and the measuring ranges may be switched over automatically.The measuring error is equal to or less than 0.1%.
标签: development introduced designed software
上传时间: 2016-04-09
上传用户:stewart·
This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 clock is set to 14 MHz.
标签: continuously ADC describes converted
上传时间: 2014-01-02
上传用户:徐孺
中国EPC标准草案(基本上是EPC C1G2的中文翻译) 射频识别协议- 第1类第2代UHF RFID 860兆赫-960兆赫通讯协议 EPC™ Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz
标签: EPC Radio-Frequency C1G2 8482
上传时间: 2016-06-06
上传用户:上善若水
PTR2000 的Pin6 ( PWR) 与AT89C51 的P1. 0 相连,PTR2000 的Pin7 (TXEN) 与AT89C51 的P1. 1 相连,CS 直接接地,利用工作频道1 ,即433. 92 MHz. 通过汇编语言对其编程.
上传时间: 2016-06-19
上传用户:hopy
LCM(RT-240128TA)显示程序 */ /* LCM 控制芯片 T6963C 带32KRAM */ /* MCU 型号: STC 89C52RD2 */ /* 时钟频率: 11.0592 MHz */ /* 接口方式: 直接接口(总线方式
上传时间: 2016-07-17
上传用户:xuan‘nian
高性能、低功耗的 AVR® 8 位微处理器 • 先进的 RISC 结构 – 133 条指令 – 大多数可以在一个时钟周期内完成 – 32 x 8 通用工作寄存器 + 外设控制寄存器 – 全静态工作 – 工作于16 MHz 时性能高达16 MIPS
上传时间: 2016-08-10
上传用户:赵云兴