.#hw_bist.plg.1.1

Viertex 2 开发板的接口程序

@P:  Worst Slack : 992.768
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Estimated Frequency : 227.3 MHz
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Requested Frequency : 1.0 MHz
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Estimated Period : 4.399
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Requested Period : 1000.000
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Slack : 995.601
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Estimated Frequency : 158.2 MHz
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Requested Frequency : 0.3 MHz
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Estimated Period : 6.323
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Requested Period : 4000.000
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Slack : 3993.677
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Estimated Frequency : 328.0 MHz
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Requested Frequency : 1.0 MHz
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Estimated Period : 3.049
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Requested Period : 1000.000
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Slack : 996.951
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Estimated Frequency : 260.2 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Requested Frequency : 1.0 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Estimated Period : 3.844
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Requested Period : 1000.000
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Slack : 996.156
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Estimated Frequency : 313.2 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Requested Frequency : 1.0 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Estimated Period : 3.193
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Requested Period : 1000.000
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Slack : 996.807
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Estimated Frequency : 227.3 MHz
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Requested Frequency : 1.0 MHz
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Estimated Period : 4.399
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Requested Period : 1000.000
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Slack : 995.601
@P:  System - Estimated Frequency : 138.3 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 7.232
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 992.768
@P: HW_BIST Part : xc2vp2fg256-7
@P: HW_BIST I/O primitives : 131
@P: HW_BIST I/O Register bits : 0
@P: HW_BIST Register bits (Non I/O) : 580 (20%)
@P: HW_BIST Block Rams : 17 of 12 (141%)
@P: HW_BIST Total Luts : 1296 (46%)