This document describes how to switch to and program the unisersal serial bus (USB) analog phase-Locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-Locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
标签： describes unisersal document phase-lo
上传时间： 2014-01-13
上传用户：hustfanenze
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
标签： e.g. communication Transform important
上传时间： 2017-06-25
上传用户：gxf2016
What happens with your machine when you need to move away from the computer for 10 or more minutes? How secure is your data? Can someone sit on your chair while you are at a coworkers office and play with your data? Maybe you need a computer locking tool that is small and easy to use yet powerful enough to make sure your machine is Locked when you need to go out for a break.
标签： computer happens machine minutes
上传时间： 2017-08-24
上传用户：semi1981
描述 了PLL 的基础知识哦，非常的 实用
标签： Phase Locked Loop Design Fundamentals
上传时间： 2017-03-13
上传用户：rfzhangyicheng
由STC89C51单片机来控制DHT11传感器采集的温湿度的转换、1602液晶屏的显示，以及蜂鸣器的报警。
上传时间： 2018-04-27
上传用户：luson
PLL(Phase Locked Loop)： 为锁相回路或锁相环，用来统一整合时钟信号，使高频器件正常工作，如内存的存取资料等。PLL用于振荡器中的反馈技术。 许多电子设备要正常工作，通常需要外部的输入信号与内部的振荡信号同步。一般的晶振由于工艺与成本原因，做不到很高的频率，而在需要高频应用时，由相应的器件VCO，实现转成高频，但并不稳定，故利用锁相环路就可以实现稳定且高频的时钟信号。
上传时间： 2021-07-23
上传用户：紫阳帝尊
ADC模数转换器件Altium Designer AD原理图库元件库SV text has been written to file : 4.4 - ADC模数转换器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-Output-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LoopPLL10k Generic Phase Locked LoopPLL5k Generic Phase Locked LoopPLLx Generic Phase Locked Loop水位计
标签： adc 模数转换 altium designer
上传时间： 2022-03-13
上传用户：
Abstract: A sliding mode observer and fractional-order phase-Locked loop (FO-PLL) method is proposed for the sensorless speed control of a permanent magnet synchronous motor (PMSM).The saturation function is adopted in order to reduce the chattering phenomenon caused by the sliding mode observer. In this proposed FO-PLL, method, a regulable fractional order r is involved, which means that the FO-PLL provides an extra degree of freedom. In fact, the conventional phase-Locked loop (PLL) applied in sensorless PMSM control can be seen as a special case of the proposed FO-PLL. By selecting a proper fractional order r a better performance may be achieved. The computer simulation results demonstrate the effectiveness of the proposed method.Key words: fractional calculus; fractional order phase-Locked loop; sensorless control; sliding mode observer; permanent magnet synchronous motor; speed controll
上传时间： 2022-06-18
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一.基础理论锁相环路（Phase Locked Loop）是一个闭环的相位控制系统，它的输出信号的相位能自动跟踪输入信号相位。系统框图如下：当0，（1）与0：（1）相等时，两矢量以相同的角速度旋转，相对位置，即夹角维持不变，通常数值又较小，这就是环路的锁定状态。从输入信号加到锁相环路的输入端开始，一直到环路达到锁定的全过程，称为捕获过程。设系统最初进入同步状态[2nrtto，e，.]的时间为1。。那么从1=1，的起始状态到达进入同步状态的全部过程就称为锁相环路的捕获过程。捕获过程所需的时间T，=1，-1，称为捕获时间。显然，捕获时间T，的大小不但与环路的参数有关，而且与起始状态有关。对一定的环路来说，是否能通过捕获而进入同步完全取决于起始频差8.（4）-Ao。。若Ao，超过某一范围，环路就不能捕获了。这个范围的大小是锁相环路的一个重要性能指标，称为环路的捕获带Ao，。
标签： 射频锁相环
上传时间： 2022-06-21
上传用户：
