Locked
共 46 篇文章
Locked 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 46 篇文章，持续更新中。
PLL锁相环
<span style="color:#333333;font-family:arial, 宋体, sans-serif;font-size:14px;text-indent:28px;white-space:normal;background-color:#FFFFFF;">PLL(Phase Locked Loop)： 为锁相回路或</span><a target="_blank" href=
Phase-Locked+Loops+for+Wireless+Communications
This book is intended for the graduate or advanced undergraduate<br />
engineer. The primary motivation for developing the text was to present a<br />
complete tutorial of phase-locked loops with a co
Digital Phase Locked Loop
This work titled A Digital Phase Locked Loop based Signal and Symbol Recovery<br />
System for Wireless Channel is intended to serve as a document covering funda-<br />
mental concepts and application
DHT11温湿度检测
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<span style="mso-spacerun:'yes';font-family:宋体;font-size:12.0000pt;mso-font-kerning:1.0000pt;"><span style="font-family:宋体;">由</span></span><span style="mso-spacerun:'yes';font-
another phase locked example for matlab
another phase locked example for matlab
What happens with your machine when you need to move away from the computer for 10 or more minutes?
What happens with your machine when you need to move away from the computer for 10 or more minutes? How secure is your data? Can someone sit on your chair while you are at a coworkers office and play
The Hilbert Transform is an important component in communication systems, e.g. for single sideband m
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operat
Phase Locked Loop Design Fundamentals
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描述 了PLL 的基础知识哦，非常的 实用
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ADPLL of high level phase locked loop
ADPLL of high level phase locked loop
％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated
％The phase locked loop(PLL),adjusts the phase of a local oscillator
％w.r.t the incoming modulated signal.In this way,the phase of the
％incoming signal is locked and the signal is demodulated.This
模拟cmos集成电路设计(design of analog
<P>模拟集成电路的设计与其说是一门技术，还不如说是一门艺术。它比数字集成电路设计需要更严格的分析和更丰富的直觉。严谨坚实的理论无疑是严格分析能力的基石，而设计者的实践经验无疑是诞生丰富直觉的源泉。这也正足初学者对学习模拟集成电路设计感到困惑并难以驾驭的根本原因。.<BR>美国加州大学洛杉机分校(UCLA)Razavi教授凭借着他在美国多所著名大学执教多年的丰富教学经验和在世界知名顶级公司(AT&
XAPP854-数字锁相环(DPLL)参考设计
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Many applications require a clock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another clock. This type of clock circuit is important in
寄存器和环路滤波器的设计
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The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthe
This file is used to develop Phase locked loop.
This file is used to develop Phase locked loop.
CD4046 phase-locked loop induction heating power supply in the application of induction heating
CD4046 phase-locked loop induction heating power supply in the application of induction heating
DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDR
A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops
A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops
Very good code for Phase locked Loop in matlab
Very good code for Phase locked Loop in matlab
This document describes how to switch to and program the unisersal serial bus (USB) analog phase-lo
This document describes how to switch to and program the unisersal serial bus (USB)
analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example
assembly programs for programming and s
开关稳压器的偏置低噪声变容
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Telecommunication, satellite links and set-top boxes allrequire tuning a high frequency oscillator. The actualtuning element is a varactor diode, a 2-terminal device thatchanges