Locked
共 46 篇文章
Locked 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 46 篇文章，持续更新中。
Pll Performance Simulation And Design Handbook
This book is intended for the reader who wishes to gain a solid understanding of Phase Locked Loop architectures and their applications. It provides a unique balance between both theoretical perspecti
Specifying the Jitter Performance
The question of sample-clock quality is a perennial one for digital audio equipment designers. Yet most chip makers
provide very little information about the jitter performance of their products. Con
MC44144数据手册
The MC44144 is a gated phase–locked loop intended for, but not
restricted to, video applications.
单片机控制的全数字锁相直流调速系
锁相环调速系统的工作原理所谓锁相环PLL(phase Loop Locked)是能完成两个频率信号相位同步的负反馈自动控制系统,它有三个基本单元;相位比较器、压控振荡器和低通滤波器.
Phase-Locked Loop Circuit Design
·Phase-Locked Loop Circuit Design
单片机控制的全数字锁相直流调速
锁相环调速系统的工作原理所谓锁相环PLL(phase Loop Locked)是能完成两个频率信号相位同步的负反馈自动控制系统,它有三个基本单元;相位比较器、压控振荡器和低通滤波器.
基于VXI总线用DDS+PLL技术实现精密时钟源
DDS（直接数字频率合成）技术是一门在频率合成领域的新兴技术，具有响应时间短，<BR>精度高等优点。而PLL（Phase Locked Loop）锁相环技术虽然工作速度慢，但稳定可靠。VXI 总线具有
SA8025锁相环频率合成器性能简介 设计实例及常见问题的解答
The SA8025 is a 3V, 1.8GHz, SSOP 20-pin packaged fractional-N<BR>phase locked-loop (PLL) frequency s
锁相环理论教程,PLL Theory Tutorial
<P>This tutorials discusses the key areas of Phase Locked Loop (PLL) design, covering the main compo
4046 CMOS PLL 锁相环电路
<P>The CD4046BC micropower phase-locked loop (PLL) consists<BR>of a low power, linear, voltage-contr
应用UMA1014T锁相环合成器设计一个锁相环电路
This application note is intended as a guide to designing a phase<BR>locked loop based on the Philip
循环过滤器配置为MAX3670低抖动PLL频率参考时钟发生器
Abstract: The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses a
以MPC505 PC509为例,介绍在微控制器应用中锁相环性能的通用问题及避免锁相环性能降级问题的建议
Microcontroller-based applications can be delayed or jeopardized by<BR>reduced phase locked loop (PL
MC145170在基本HF和VHF振荡器中的应用电路
Phase–locked loop (PLL) frequency synthesizers are commonly<BR>found in communication gear today. Th
Android---Locked-Out
<p>Android---Locked-Out，有需要的可以参考！</p>
Phase-Locked Loops for Wireless Communications (英).pdf
资料->【E】光盘论文->【E5】英文书籍->Phase-Locked Loops for Wireless Communications (英).pdf
应用于FPGA芯片时钟管理的锁相环设计实现
<p>该文档为应用于FPGA芯片时钟管理的锁相环设计实现讲解文档</p><p>摘 要: 设计了一种嵌入于 FPGA 芯片的锁相环, 实现了四相位时钟、倍频、半整数可编程分频、可调节相位输出
功能, 满足对于 FPGA 芯片时钟管理的要求. 锁相环采用了自偏置结构, 拓展了锁相环的工作范围, 缩短了锁定时
间, 其阻尼系数以及环路带宽和工作频率的比值都仅由电容的比值决定, 有效地减小了工艺、电压
射频锁相环基础理论
<p>一.基础理论</p><p>锁相环路（Phase Locked Loop）是一个闭环的相位控制系统，它的输出信号的相位能自动跟踪输入信号相位。系统框图如下：</p><p>当0，（1）与0：（1）相等时，两矢量以相同的角速度旋转，相对位置，即夹角维持不变，通常数值又较小，这就是环路的锁定状态。</p><p>从输入信号加到锁相环路的输入端开始，一直到环路达到锁定的全过程，称为捕获过程。设系统最初进
基于滑模观测器与分数阶锁相环的无传感器PMSM矢量控制
<p>Abstract: A sliding mode observer and fractional-order phase-locked loop (FO-PLL) method is proposed for the sensorless speed control of a permanent magnet synchronous motor (PMSM).</p><p>The satur
ADC模数转换器件Altium Designer AD原理图库元件库
<p>ADC模数转换器件Altium Designer AD原理图库元件库</p><p>SV text has been written to file : 4.4 - ADC模数转换器件.csv</p><p><br/></p><p>Library Component Count : 29</p><p><br/></p><p>Name &nbs