Create a 1-Wire Master with Xilinx PicoBlaze
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to...
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to...
AstroII-EVB-F1K(A)-L144开发板用户指南 ...
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mi...
针对固定码长Turbo码适应性差的缺点,以LTE为应用背景,提出了一种帧长可配置的Turbo编译码器的FPGA实现方案。该设计可以依据具体的信道环境和速率要求调节信息帧长,平衡译码性能和系统时延。方案采用“自顶向下”的设计思想和“自底而上”的实现方法,对 Turbo编译码系统模块化设计后优化统一,经...
为满足TD-LTE系统对实时性的要求,通过对媒体接入控制(MAC)层和物理层之间的实时性研究以及对操作系统Nucleus PLUS的机制分析,实现了MAC层子帧调度。根据TD-LTE无线综合测试仪中的设计要求,详细介绍了Nucleus PLUS任务循环调度以及MAC子帧调度的流程设计。在实现MAC层...