This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上传时间： 2013-10-09
上传用户：evil
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上传时间： 2015-01-02
上传用户：zhangyi99104144
摘要: 串行传输技术具有更高的传输速率和更低的设计成本, 已成为业界首选, 被广泛应用于高速通信领域。提出了一种新的高速串行传输接口的设计方案, 改进了Aurora 协议数据帧格式定义的弊端, 并采用高速串行收发器Rocket I/O, 实现数据率为2.5 Gbps的高速串行传输。关键词: 高速串行传输; Rocket I/O; Aurora 协议 为促使FPGA 芯片与串行传输技术更好地结合以满足市场需求, Xilinx 公司适时推出了内嵌高速串行收发器RocketI/O 的Virtex II Pro 系列FPGA 和可升级的小型链路层协议———Aurora 协议。Rocket I/O支持从622 Mbps 至3.125 Gbps的全双工传输速率, 还具有8 B/10 B 编解码、时钟生成及恢复等功能, 可以理想地适用于芯片之间或背板的高速串行数据传输。Aurora 协议是为专有上层协议或行业标准的上层协议提供透明接口的第一款串行互连协议, 可用于高速线性通路之间的点到点串行数据传输, 同时其可扩展的带宽, 为系统设计人员提供了所需要的灵活性[4]。但该协议帧格式的定义存在弊端,会导致系统资源的浪费。本文提出的设计方案可以改进Aurora 协议的固有缺陷,提高系统性能, 实现数据率为2.5 Gbps 的高速串行传输, 具有良好的可行性和广阔的应用前景。
上传时间： 2013-10-13
上传用户：lml1234lml
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上传时间： 2013-11-02
上传用户：18862121743
解压密码：www.elecfans.com 随着微电子技术的迅速发展以及集成电路规模不断提高，对电路性能的设计 要求越来越严格，这势必对用于大规模集成电路设计的EDA 工具提出越来越高的 要求。自1972 年美国加利福尼亚大学柏克莱分校电机工程和计算机科学系开发 的用于集成电路性能分析的电路模拟程序SPICE（Simulation Program with IC Emphasis）诞生以来，为适应现代微电子工业的发展，各种用于集成电路设计的 电路模拟分析工具不断涌现。HSPICE 是Meta-Software 公司为集成电路设计中 的稳态分析，瞬态分析和频域分析等电路性能的模拟分析而开发的一个商业化通 用电路模拟程序，它在柏克莱的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它电路分析软件的基础上，又加入了一些新的功能，经 过不断的改进，目前已被许多公司、大学和研究开发机构广泛应用。HSPICE 可 与许多主要的EDA 设计工具，诸如Candence,Workview 等兼容，能提供许多重要 的针对集成电路性能的电路仿真和设计结果。采用HSPICE 软件可以在直流到高 于100MHz 的微波频率范围内对电路作精确的仿真、分析和优化。在实际应用中， HSPICE能提供关键性的电路模拟和设计方案，并且应用HSPICE进行电路模拟时， 其电路规模仅取决于用户计算机的实际存储器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
上传时间： 2013-10-18
上传用户：s363994250
Abstract: This application note discusses the REF pin functionality in the indirect current-feedbackarchitecture for instrumentation amplifiers. This article compares the importance of a REF buffer in a
上传时间： 2015-01-03
上传用户：时代将军
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
Have you had the exasperating experience of a laptop orPDA defi antly not responding to your commands? Youfrantically press key after key, but to no avail. As hopeturns to anger (but just before you throw the company’slaptop through the window) you slam your fi nger againstthe on/off power button. Ten seconds later, your laptopfi nally surrenders and the screen goes black in a highpitched whimper.
上传时间： 2013-12-10
上传用户：Vici
Frequently, voltage reference stability and noise defi nemeasurement limits in instrumentation systems. In particular,reference noise often sets stable resolution limits.Reference voltages have decreased with the continuingdrop in system power supply voltages, making referencenoise increasingly important. The compressed signalprocessing range mandates a commensurate reductionin reference noise to maintain resolution. Noise ultimatelytranslates into quantization uncertainty in A to D converters,introducing jitter in applications such as scales, inertialnavigation systems, infrared thermography, DVMs andmedical imaging apparatus. A new low voltage reference,the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT.Figure 1 lists salient specifi cations in tabular form. Accuracyand temperature coeffi cient are characteristic ofhigh grade, low voltage references. 0.1Hz to 10Hz noise,particularly noteworthy, is unequalled by any low voltageelectronic reference.
上传时间： 2013-10-30
上传用户：wxhwjf
