Nios II 软件开发人员手册中的缓存和紧耦合存储器部分 Nios® II embedded processor cores can contain Instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上传时间： 2013-10-25
上传用户：虫虫虫虫虫虫
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom Instructions to the Nios II processor Instruction set. Using custom Instructions, you can reduce a complex sequence of standard Instructions to a single Instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom Instructions to the Nios II processor. The custom Instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-11
上传用户：kang1923
介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller Instruction set, with many new 8, 16 and 32 bit Instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
标签： architecture introducin peripheral improves
上传时间： 2015-03-15
上传用户：ccclll
Here are some short Instructions for use of mod-xslt. The stylesheet is specified using the Processing Instruction <?xml-stylesheet type="text/xsl" href="URL-OF-YOUR-STYLESHEET"?> or now new <?xslt-stylesheet agent="THE-USER-AGENT-STRING-OF-THE-BROWSER" href="URL-OF-YOUR-STYLESHEET"?> This now enables you to use different Stylesheets for different browsers. (For example Netscape & IE) (or Web & WAP for that matter)
标签： Instructions stylesheet specified mod-xslt
上传时间： 2014-01-14
上传用户：as275944189
The ability to write efficient, high-speed arithmetic routines ultimately depends upon your knowledge of the elements of arithmetic as they exist on a computer. That conclusion and this book are the result of a long and frustrating search for information on writing arithmetic routines for real-time embedded systems. With Instruction cycle times coming down and clock rates going up, it would seem that speed is not a problem in writing fast routines. In addition, math coprocessors are becoming more popular and less expensive than ever before and are readily available. These factors make arithmetic easier and faster to use and implement. However, for many of you the systems that you are working on do not include the latest chips or the faster processors. Some of the most widely used microcontrollers used today are not Digital Signal Processors (DSP), but simple eight-bit controllers such as the Intel 8051 or 8048 microprocessors.
标签： arithmetic high-speed ultimately efficient
上传时间： 2014-11-30
上传用户：lizhen9880
ARMask.The ARM has six operating modes: • User (unprivileged mode under which most tasks run) • FIQ (entered when a high priority (fast) interrupt is raised) • IRQ (entered when a low priority (normal) interrupt is raised) • Supervisor (entered on reset and when a Software Interrupt Instruction is executed) • Abort (used to handle memory access violations) • Undef (used to handle undefined Instructions) * ARM Architecture Version 4 adds a seventh mode: • System (privileged mode using the same registers as user mode)
标签： unprivileged operating ARMask modes
上传时间： 2013-12-24
上传用户：bcjtao
The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-Instruction-word (VLIW) architecture (VelociTI.2™ ) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
标签： highest-performance fixed-point TMS 320
上传时间： 2013-12-21
上传用户：watch100
/*SPI规范：Data is always clocked into the device on the rising edge of SCK a-*/ /* nd clocked out of the device on the falling edge of SCK.All Instruction-*/ /* s,addresses and data are transferred with the most significant bit(MSB) */ /* first.
上传时间： 2016-02-19
上传用户：远远ssad
this a 8-bit risc micro process,Th eM C Ud esignedis c ompatiblew ith PIC16C57 o microchip Technology Inc.in the Instruction system
标签： ompatiblew Technolog esignedis microchip
上传时间： 2014-01-13
上传用户：xinyuzhiqiwuwu
The SST89E516RDx and SST89V516RDx are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 Instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
标签： microcontroller SST 516 RDx
上传时间： 2014-01-07
上传用户：笨小孩
