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Content Addressable Memory 的verilog源代码。经过modelsim仿真。
256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
SD 2.0 Memory Controller SD Bus Interface SD Controller Logic NAND Flash Controller
XILINX memory interface generator. XILINX的外部存储器接口。
detailed memory test for embedded systems, checks for shorted address/data lines too
资料->【E】光盘论文->【E5】英文书籍->High Performance Memory Testing Design Principles, Fault Modeling and Self-Test (英).pdf
simple client/server in socket and fifo in c better run in linux.
These directories contain the examples from Database Programming withJDBC and Java, 2nd Edition.