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  • LabVIEW for Everyone(经典英文书籍)

    The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8!   Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through careFULLY explained, step-by-step examples that give you reusable code for your own projects!   This brand-new Third Edition has been FULLY revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!

    标签: Everyone LabVIEW for 英文

    上传时间: 2013-10-14

    上传用户:shawvi

  • 通过整合硬件分立收发器简化AISG的控制系统

    Abstract: This article describes the Antenna Interface Standards Group (AISG) standard in telecommunications and details itshardware implementation. It explains how a FULLY integrated transceiver such as the MAX9947 can help reduce space and cost, andsolve bus arbitrations in base-station tower equipment.

    标签: AISG 硬件 分立收发器 控制系统

    上传时间: 2014-12-30

    上传用户:wangchong

  • 《射频集成电路设计基础》讲义

     关于射频(RF) 关于射频集成电路 无线通信与射频集成电路设计 课程相关信息 RFIC相关IEEE/IEE期刊和会议• 是什么推动了RFIC 的发展?• Why RFIC?– Why IC?– 体积更小,功耗更低,更便宜→ 移动性、个人化、低成本– 功能更强,适合于复杂的现代通信网络– 更广泛的应用领域如生物芯片、RFID 等• Quiz: why not FULLY integrated?• 射频集成电路设计最具挑战性之处在于,设计者向上必须懂得无线系统的知识,向下必须具备集成电路物理和工艺基础,既要掌握模拟电路的设计和分析技巧,又要熟悉射频和微波的理论与技术。(当然,高技术应该带来高收益:)

    标签: 射频集成 电路设计 讲义

    上传时间: 2014-05-08

    上传用户:liuchee

  • XAPP953-二维列序滤波器的实现

      This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a FULLY synchronous interface through the ce, clk,and rst ports.

    标签: XAPP 953 二维 滤波器

    上传时间: 2013-12-13

    上传用户:逗逗666

  • WP312-Xilinx新一代28nm FPGA技术简介

    Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a FULLY programmable alternative to ASSPs and ASICs.

    标签: Xilinx FPGA 312 WP

    上传时间: 2013-12-07

    上传用户:bruce

  • Verilog编码中的非阻塞性赋值

      One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not FULLY understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

    标签: Verilog 编码 非阻塞性赋值

    上传时间: 2013-11-01

    上传用户:xzt

  • CoLIN 人工语言模拟 汉化版 2002年8月9日 原作者 布朗 alan j. brown 15 Kinloch Road Renfrew Scotland PA4

    CoLIN 人工语言模拟 汉化版 2002年8月9日 原作者 布朗 alan j. brown 15 Kinloch Road Renfrew Scotland PA4 0RJ alan@barc0de.demon.co.uk http://www.barc0de.demon.co.uk/ 汉化者 陈辉 主页: http://go2debug.yeah.net 邮件: go2debug@hotmail.com ICQ: 149054569 简介 通过菜单可以清空数据库。 程序会从你的输入中学习,如果你不想这样,就请关闭学习功能。 原作者声明 This program is giftware. If you like it send me something nice. Copyright is FULLY reserved by Alan J. Brown, any program developed from the CoLIN source code must give Alan J. Brown appropriate credit. 更多问题 请到我的主页 http://go2debug.yeah.net 或者给我发信 go2debug@hotmail.com 另外在布朗的主页上有留言板

    标签: j. Scotland Kinloch Renfrew

    上传时间: 2014-01-20

    上传用户:彭玖华

  • This program uses the database created by MakeAPIDB. It opens a connection * to a database using t

    This program uses the database created by MakeAPIDB. It opens a connection * to a database using the same property file used by MakeAPIDB. Then it * queries that database in several interesting ways to obtain useful * information about Java APIs. It can be used to look up the FULLY-qualified * name of a member, class, or package, or it can be used to list the members * of a class or package.

    标签: database connection MakeAPIDB program

    上传时间: 2013-11-25

    上传用户:miaochun888

  • Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP

    Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • FULLY Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag

    标签: 8226 Programmable Compatible In-System

    上传时间: 2015-06-27

    上传用户:dianxin61

  • This PNG Delphi version 1.56 documentation (this version is a major rewrite intended to replace the

    This PNG Delphi version 1.56 documentation (this version is a major rewrite intended to replace the previous version, 1.2). Improvements in this new version includes: This new version allows the programmer to not use Delphi heavy units which will greatly reduce the size of the final executable. Read more about this feature here. Most, if not all, Portable Network Graphics features as CRC checking are now FULLY performed. Error on broken images are now better handled using new exception classes. The images may be saved using interlaced mode also. Transparency information won t be discarted after the image is loaded any more. Most of the images are decoded much faster now. The images will be better encoded using fresh new algorithms. IMPORTANT! Now transparency information is used to display images.

    标签: version documentation intended rewrite

    上传时间: 2015-06-28

    上传用户:qiao8960