源码文件
The schematic is at foler schematic. The hex file is at foler default. You can compiler the code yourself using AvrStudio4.13…
FPGA+Schematic 源代码
汇集 FPGA+Schematic 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
收录资源 500 份
全站深度检索
共匹配 500 份工程资源
· 第 38 / 50 页
源码文件
JDF B // Created by Version 2.0 PROJECT Simple 4x1 MUX - Mixed Sch/VHDL Design DESIGN mux4x1_mixed Normal DEVKIT ispLSI5256VE…
源码文件
//! ************************************************************************** // Written by: Map H.42 on Thu Aug 16 10:31:04 200…
源码文件
SCHEMATIC START ; // created by map version G.35 on Sat Apr 22 18:29:59 2006 COMP "clk" LOCATE = SITE "P77" LEVEL 1; COMP "s…
源码文件
The schematic is at foler schematic. The hex file is at foler default. You can compiler the code yourself using AvrStudio4.13…
源码文件
SCHEMATIC START ; // created by map version G.23 on Sun Jul 16 15:25:26 2006 COMP "N" LOCATE = SITE "P96" LEVEL 1; COMP "N" …
源码文件
# XST (Creating Lso File) : light.lso # xst flow : RunXST light.syr light.prj light.sprj light.ana light.stx light.cmd_lo…
源码文件
SCHEMATIC START ; // created by map version G.23 on Sat Aug 02 12:56:23 2008 NET "rclk_BUFGP/IBUFG" BEL "rclk_BUFGP/BUFG.GCLKMU…
源码文件
//: C16:Drawing.cpp // From Thinking in C++, 2nd Edition // Available at http://www.BruceEckel.com // (c) Bruce Eckel 2000 // …
源码文件
SCHEMATIC START ; # map: version ispLever_v61_PROD_Build (37) -- WARNING: Map write only section -- Tue Jul 17 10:48:28 2007 …