关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
OLE Programmer s Reference Information in this online help system is subject to change without notice and does not represent a commitment on the part of Microsoft Corporation. The software and/or files described in this online help system are furnished under a license agreement or nondisclosure agreement. The software and/or files may be used or copied only in accordance with the terms of the agreement. The purchaser may make one copy of the software for backup purposes. No part of this online help system may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or information and retrieval systems, for any purpose other than the purchaser s personal use, without the written permission of Microsoft Corporation.
标签： Information Programmer Reference subject
上传时间： 2015-08-04
上传用户：hxy200501
ACM试题An Easy Problem Description As we known, data stored in the computers is in binary form. The problem we discuss now is about the positive integers and its binary form. Given a positive integer I, you task is to find out an integer J, which is the minimum integer greater than I, and the number of 1 s in whose binary form is the same as that in the binary form of I. For example, if "78" is given, we can write out its binary form, "1001110". This binary form has 4 1 s. The minimum integer, which is greater than "1001110" and also contains 4 1 s, is "1010011", i.e. "83", so you should output "83".
标签： Description computers Problem binary
上传时间： 2013-12-11
上传用户：libenshu01
A six people s rushing replies an implement, use some s switches in toggle switch K0 ~ K5 is that ON accomplishes when rushing to reply button , nobody rush to answer, 6 numerical code circulation takes turns at demonstrating 1 ~ 6 (horse races) , who rushes to reply the numerical code stops having a ride on a horse , first, whose serial number, has simultaneous light of 6 numerical codes again afterwards the key presses down. System denies responding to, until this place is OFF batch , the wheel restoring 1 ~ 6 horse races starting time as soon as rushes to answer.
标签： implement switches rushing replies
上传时间： 2013-12-27
上传用户：l254587896
RTL-lwIP is the porting of the lwIP TCP/IP stack to RTLinux-GPL.The focus of the RTL-lwIP stack is to reduce memory usage and code size, making RTL-lwIP suitable for use in small clients with very limited resources such as embedded systems.
标签： RTL-lwIP the stack RTLinux-GPL
上传时间： 2015-09-05
上传用户：
THIS CODE IS FOR EXAMPLE PURPOSES ONLY, USE AT YOUR OWN RISK, NO WARRANTY IS ASSUMED OR IMPLIED The intension of this code is to provide an example of attaching to the MUX layer with a custom ethernet protocol. Though the NPT code is provided for handling alternate frames, it has not been tested.
标签： PURPOSES WARRANTY ASSUMED EXAMPLE
上传时间： 2015-09-21
上传用户：qq521
This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different area/performance tradeoffs.
标签： capabilities exploration AccelDSP exercise
上传时间： 2014-12-22
上传用户：eclipse
The intended use of this help manual is a quick reference guide as it is not fully inclusive of all elements of the PL/SQL Programming Language. Please refer to the PL/SQL User s Guide and Reference for more information.
标签： inclusive reference intended manual
上传时间： 2014-01-26
上传用户：lnnn30
his paper provides a tutorial and survey of methods for parameterizing surfaces with a view to applications in geometric modelling and computer graphics. We gather various concepts from di® erential geometry which are relevant to surface mapping and use them to understand the strengths and weaknesses of the many methods for parameterizing piecewise linear surfaces and their relationship to one another.
标签： parameterizing provides tutorial surfaces
上传时间： 2014-11-09
上传用户：努力努力再努力
Developers use algorithms and data structures every day of their working lives. Having a good under-standing of these algorithms and knowledge of when to apply them is essential to producing softwarethat not only works correctly, but also performs efficiently. This book aims to explain those algorithms and data structures most commonly encountered in day-to-day software development, while remaining at all times practical, concise, and to the point, with little orno verbiage to distract from the core concepts and examples.
标签： Developers algorithms structures working
上传时间： 2015-11-03
上传用户：wyc199288
