Development+Process 源代码

汇集 Development+Process 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。

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源码文件

/* * project: CTA-model of Fischer's mutual exclusion protocol. * modules: Process, System * author: Dirk Beyer, 2000 * last…

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY square IS PORT(clk0,fq:IN STD_LOGIC; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sin IS PORT(clk0,fq:in std_logic; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk0,fq:IN STD_LOGIC; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY square IS PORT(clk0,fq:IN STD_LOGIC; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sin IS PORT(clk0,fq:in std_logic; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY delta IS PORT(clk0,fq:IN STD_LOGIC…

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk0,fq:IN STD_LOGIC; …

源码文件

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY delta IS PORT(clk0,fq:IN STD_LOGIC…

源码文件

Example code from Perl for System Administration by David N. Blank-Edelman O'Reilly and Associates, 1st Edition, ISBN 1-56592-609…