虚拟串口软件
标签： Virtual Serial Driver Port
上传时间： 2013-10-27
上传用户：1234321@q
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-11-23
上传用户：truth12
虚拟串口软件
标签： Virtual Serial Driver Port
上传时间： 2013-10-23
上传用户：JIUSHICHEN
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
3 FPGA设计流程 完整的FPGA 设计流程包括逻辑电路设计输入、功能仿真、综合及时序分析、实现、加载配置、调试。FPGA 配置就是将特定的应用程序设计按FPGA设计流程转化为数据位流加载到FPGA 的内部存储器中，实现特定逻辑功能的过程。由于FPGA 电路的内部存储器都是基于RAM 工艺的，所以当FPGA电路电源掉电后，内部存储器中已加载的位流数据将随之丢失。所以，通常将设计完成的FPGA 位流数据存于外部存储器中，每次上电自动进行FPGA电路配置加载。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100电路为例，FPGA的配置模式有四种方案可选择：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通过芯片上的一组专/ 复用引脚信号完成的，主要配置功能信号如下： (1)M0、M1、M2：下载配置模式选择; (2)CLK：配置时钟信号; (3)DONE：显示配置状态、控制器件启动;
上传时间： 2013-11-18
上传用户：oojj
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
上传时间： 2015-01-02
上传用户：时代将军
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2013-10-28
上传用户：jyycc
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-20
上传用户：dave520l
这个软件需要你的本机操作的。其他机器是算不出来的！ 就是说 一台电脑只有一个注册码对应！ 这里有个办法： MULTISIM2001安装方法： 一：运行SETUP.EXE安装。在安装时，要重新启动计算机一次。 二：启动后在“开始>程序”中找到STARTUP项，运行后，继续进行安装，安装过程中，第一次要求输入“CODE"码时， 输入“PP-0411-48015-7464-32084"输入后，会提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO." 按确定，又会出现一个“feature code”框，输入“FC-6424-04180-0044-13881”后， 在弹出的对话框中选择“取消”，一路确定即可完成安装。 三：1.运行VERILOG目录内的SETUP安装 2.运行FPGA目录内的SETUP安装 3.将CRACK目录内的LICMGR.DLL拷贝到WINDOWS系统的SYSTEM 目录内 4.并将VERILOG安装目录内的同名文件删除 5.将SILOS.LIC文件拷到VERILOG安装目录内覆盖原文件，并作如下编辑： 6.将“COMPUTER_NAME”替换为你的机器名 7.将“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替换为你的 实际安装路径。如此你便可以使用VERILOG了。 四：安装之后，运行MULTISIM2001,会要求输入“RELEASE CODE",不用着急， 记下“SERIAL NUMBER"和“SIGNATURE NUMBER", 使用CRACK目录内的注册器“MULTISIM KEYGEN.EXE" 将刚才记下的两个号码分别填入后， 即可得到"RELEASE CODE", 以后就可以正常使用了。 五：接下来运行 database update目录中的几个文件， 进行数据库合并即可。祝你成功！！ 六：启动MULTISIM2001时候的注册码 1： PP-0411-48015-7464-32084 2： 37506-86380 3:的三个空格 1975 2711 4842 里面包含了：Multisim2001汉化破解版、Multisim.V10.0.1.汉化破解版图解 解压密码：www.pp51.com
上传时间： 2013-11-16
上传用户：天空说我在
